阻塞式与非阻塞式的区别仿真

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原创最新推荐文章于 2026-08-01 13:51:34 发布 617 阅读 AI 写同款· GEO 优化 ›

FPGA学习 -通过波形图来看阻塞赋值和非阻塞赋值的区别本文章采用阻塞赋值和非阻塞赋值对比的方式来讨论二者的区别，利用简单的例程+波形图直观查看细小差别。 1.模块文件： module block_nonblock(clk50M,rst_n,a,b,c,out); input clk50M; input rst_n; input a; //实现a+b+c=out，拆分成两部。一步是定义d且d=a+b，另一布是out=c+d input b; input c; output reg [1:0]out; //out 阅读详情

阻塞式源代码：

module block(
	//input 
	clk,
	rst_n,
	//output 
	result_o,
	a,
	b 
);
input clk,rst_n;

output reg [4:0] result_o;
output reg [3:0] a,b;
always @(posedge clk )
	begin 
		if(!rst_n)
			begin
				a = 4'd0;
				b = 4'd0;
			end 
		else 
			begin 
				a = 4'd2;
				b = b + 1'b1;
				result_o = a + b + 1'b1;
			end 
	end 

endmodule

阻塞式测试代码：

`timescale 1 ns/ 1 ns
module block_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires                                               
wire [3:0]  a;
wire [3:0]  b;
wire [4:0]  result_o;
parameter CLK_PERIOD = 20;
// assign statements (if any)                          
block i1 (
// port map - connection between master ports and signals/registers   
	.a(a),
	.b(b),
	.clk(clk),
	.result_o(result_o),
	.rst_n(rst_n)
);
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
	clk = 1'b0;
	rst_n = 1'b0;
	#(CLK_PERIOD*5) rst_n = 1'b1;
	#(CLK_PERIOD*5) $stop;
// --> end                                             
$display("Running testbench");                       
end  

always  #(CLK_PERIOD/2) clk = ~clk; 
                                                            
always                                                 
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
// code executes for every event on sensitivity list   
// insert code here --> begin                          
                                          
@eachvec;                                              
// --> end                                             
end                                                    
endmodule

阻塞式仿真波形：

非阻塞式代码：

module block_un(
	//input 
	clk,
	rst_n,
	//output 
	result_o,
	a,
	b 
);
input clk,rst_n;

output reg [4:0] result_o;
output reg [3:0] a,b;
always @(posedge clk )
	begin 
		if(!rst_n)
			begin
				a <= 4'd0;
				b <= 4'd0;
			end 
		else 
			begin 
				a <= 4'd2;
				b <= b + 1'b1;
				result_o <= a + b + 1'b1;
			end 
	end 

endmodule

非阻塞式测试代码：

`timescale 1 ns/ 1 ns
module block_un_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires                                               
wire [3:0]  a;
wire [3:0]  b;
wire [4:0]  result_o;

// assign statements (if any)                          
block_un i1 (
// port map - connection between master ports and signals/registers   
	.a(a),
	.b(b),
	.clk(clk),
	.result_o(result_o),
	.rst_n(rst_n)
);
parameter CLK_PERIOD = 20;
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
 	clk = 1'b0;
	rst_n = 1'b0;
	#(CLK_PERIOD*5) rst_n = 1'b1;
	#(CLK_PERIOD*5) $stop;
// --> end                                             
$display("Running testbench");                       
end  

always  #(CLK_PERIOD/2) clk = ~clk;                                                 
always                                                 
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
// code executes for every event on sensitivity list   
// insert code here --> begin                          
                                                       
@eachvec;                                              
// --> end                                             
end                                                    
endmodule

非阻塞式仿真波形：