how to set wire value in always block

francisco_flynn

于 2021-03-28 21:38:58 发布

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分类专栏： FPGA

本文链接：https://blog.youkuaiyun.com/weixin_43780260/article/details/115288370

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这篇博客探讨了Verilog中两种赋值方式的区别：Blocking和Non-Blocking。通过示例代码`assign test=input;`和`always@* test=input;`，解释了它们在行为上的差异。文章强调了在组合逻辑和时序逻辑中使用不同赋值方式的重要性，并提出了两条经验规则：1) 对于组合逻辑和级联敏感代码，以及时钟分配，应使用Blocking赋值；2) 对于在时钟边沿写入并在同一边沿读取的变量，应使用Non-Blocking赋值。

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wire test;
//At all times, test equals input
assign test = input;

has the same behaviour as:

reg test;
//Each time input changes(with the always@*), test takes its value
always@*
  test = input;

there are two experience rule:

Always use blocking assignments for combinatorial or level-sensitive code, as well a clock assignments
Always use non-blocking assignments for variables that are written on a clock edge, and read on the same clock edge in another process.