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【HDLBits 刷题】所有答案直达链接汇总

作用： 提供了一种描述真值表的描述方式可以描述有限状态机 区别： case是一一对应，即0、1、x、z分别对应0、1、x、z；当执行到对应项后，case就会退出casex是将高阻值（z）和不定值（x）都视为不关心的状态，即出现x或z会匹配任意0、1、x、z状态；casez是将高阻值（z）视为不关心的状态，即出现z会匹配任意0、1...

网址：https://hdlbits.01xz.net/wiki/Count_clock自己写：module top_module( input clk, input reset, input ena, output pm, output [7:0] hh, output [7:0] mm, output [7:0] ss); always@(posedge clk ) if (reset == 1'b1)

网址：https://hdlbits.01xz.net/wiki/Fsm_onehotmodule top_module( input in, input [9:0] state, output [9:0] next_state, output out1, output out2); parameter S0 = 0, S1 =1, S2 =2, S3 = 3, S4 = 4, S5 = 5, S6 = 6, S7 = 7, S8 = 8

网址：https://hdlbits.01xz.net/wiki/Shift4module top_module( input clk, input areset, // async active-high reset to zero input load, input ena, input [3:0] data, output reg [3:0] q); always@(posedge clk or posedge areset)be

网址：https://hdlbits.01xz.net/wiki/Rotate100module top_module( input clk, input load, input [1:0] ena, input [99:0] data, output reg [99:0] q); always@(posedge clk)begin if(load == 1'b1) q <= data;

网址：https://hdlbits.01xz.net/wiki/Countbcdmodule bcdcount( input clk, input reset, input ena, output reg [3:0] q); always @(posedge clk)begin if (reset == 1'b1) q <= 4'b0; else if (ena == 1'b1)

网址：https://hdlbits.01xz.net/wiki/Shift18module top_module( input clk, input load, input ena, input [1:0] amount, input [63:0] data, output reg [63:0] q); always@(posedge clk)begin if(load == 1'b1) q &l

网址：https://hdlbits.01xz.net/wiki/Lfsr5module top_module( input clk, input reset, // Active-high synchronous reset to 5'h1 output [4:0] q); always@(posedge clk)begin if(reset == 1'b1) q <= 5'h1; else

网址：https://hdlbits.01xz.net/wiki/Lfsr32module top_module( input clk, input reset, // Active-high synchronous reset to 32'h1 output [31:0] q); reg [31:0] q_next; always @ (*) begin q_next = {q[0], q[31:1]}

网址：https://hdlbits.01xz.net/wiki/Exams/m2014_q4k自己写：module top_module ( input clk, input resetn, // synchronous reset input in, output out); reg r_in1; reg r_in2; reg r_in3; always@(posedge clk)begin if(

网址：https://hdlbits.01xz.net/wiki/Rule90module top_module( input clk, input load, input [511:0] data, output [511:0] q ); always @ (posedge clk) begin if (load) q <= data; else

网址：https://hdlbits.01xz.net/wiki/Rule110module top_module( input clk, input load, input [511:0] data, output [511:0] q); reg [511:0] q_l; reg [511:0] q_r; assign q_l = {1'b0, q[511:1]}; assign q_r = {q[510:0] , 1'b

网址：https://hdlbits.01xz.net/wiki/Conwaylifemodule top_module( input clk, input load, input [255:0] data, output [255:0] q ); reg [323:0] data_padding; //18*18 wire [255:0] q_next; integer i,j,neighbour_cnt; alway

网址：https://hdlbits.01xz.net/wiki/Countslowmodule top_module ( input clk, input slowena, input reset, output [3:0] q); always@(posedge clk)begin if(reset == 1'b1) q = 4'd0; else if(q == 4'd9 && slowe

网址：https://hdlbits.01xz.net/wiki/Dualedge第一种解法：module top_module ( input clk, input d, output q); reg m = 1'b0; reg n = 1'b0; always@(posedge clk) begin m = d; end always@(negedge c

网址：https://hdlbits.01xz.net/wiki/Module_posmodule top_module ( input a, input b, input c, input d, output out1, output out2); mod_a mod_a(out1,out2,a,b,c,d); endmodule

网址：https://hdlbits.01xz.net/wiki/Vector5module top_module ( input a, b, c, d, e, output [24:0] out );// // The output is XNOR of two vectors created by // concatenating and replicating the five inputs. assign out = ~{{5{a}},{5{b}},{5

网址：https://hdlbits.01xz.net/wiki/Module_addmodule top_module( input [31:0] a, input [31:0] b, output [31:0] sum); reg r_cout; reg [15:0] sum1; reg [15:0] sum2; add16 add16_inst1 ( .a (a[15:0] ),

网址：https://hdlbits.01xz.net/wiki/Gatesmodule top_module( input a, b, output out_and, output out_or, output out_xor, output out_nand, output out_nor, output out_xnor, output out_anotb); assign out_and = a & b;

网址：https://hdlbits.01xz.net/wiki/Popcount3module top_module( input [2:0] in, output [1:0] out ); //assign out = in[0]+in[1]+in[2]; assign out[0] = in[0]^in[1]^in[2]; assign out[1] = in[0]&in[1] | in[0]&in[2] | in[1]&

网址：https://hdlbits.01xz.net/wiki/Edgecapturemodule top_module ( input clk, input reset, input [31:0] in, output [31:0] out); reg [31:0] r_in; always@(posedge clk) begin r_in = in; end alwa

网址：https://hdlbits.01xz.net/wiki/Edgedetect2module top_module ( input clk, input [7:0] in, output [7:0] anyedge); reg [7:0] r_in; always@(posedge clk) begin r_in = in; end always@(posedge clk)

网址：https://hdlbits.01xz.net/wiki/Edgedetectmodule top_module ( input clk, input [7:0] in, output [7:0] pedge); reg [7:0] r_in; always@(posedge clk) begin r_in = in; end always@(posedge clk)

网址：https://hdlbits.01xz.net/wiki/Exams/2014_q4amodule top_module ( input clk, input w, R, E, L, output Q); wire temp1, temp2; assign temp1 = E ? w:Q; assign temp2 = L ? R:temp1; //与上题类似，不做赘述 always @ (posedge clk)

网址：https://hdlbits.01xz.net/wiki/Dff16emodule top_module ( input clk, input resetn, input [1:0] byteena, input [15:0] d, output [15:0] q); always@(posedge clk) begin if(!resetn) q = 16'd0;

网址：https://hdlbits.01xz.net/wiki/Gatesvmodule top_module( input [3:0] in, output [2:0] out_both, output [3:1] out_any, output [3:0] out_different ); //assign out_both[2:0] = {in[2]&in[3],in[1]&in[2],in[0]&in[1]};

网址：https://hdlbits.01xz.net/wiki/Gatesv100module top_module( input [99:0] in, output [98:0] out_both, output [99:1] out_any, output [99:0] out_different ); assign out_both = in[98:0] & in[99:1]; assign out_any = in[99:1] |

网址：https://hdlbits.01xz.net/wiki/Mux256to1vmodule top_module( input [1023:0] in, input [7:0] sel, output [3:0] out ); //------------------"+:"-------------- //data[begin +: width] //data[(begin + width -1): begin]//这里是上式的等价表达式 //----

网址：https://hdlbits.01xz.net/wiki/Kmap3#module top_module( input a, input b, input c, input d, output out ); assign out = a | (~b & c); //b为无关项endmodule

网址：https://hdlbits.01xz.net/wiki/Bcdadd4module top_module( input [15:0] a, b, input cin, output cout, output [15:0] sum ); wire cout1; wire cout2; wire cout3; bcd_fadd bcd_fadd_inst1 ( .a (a[3:0

网址：https://hdlbits.01xz.net/wiki/Exams/ece241_2014_q1cmodule top_module ( input [7:0] a, input [7:0] b, output [7:0] s, output overflow); // assign s = a + b; assign overflow = (a[7] & b[7] & ~s[7]) | (~a[7] & ~b[7]

网址：https://hdlbits.01xz.net/wiki/Vector4module top_module ( input [7:0] in, output [31:0] out );// assign out = {{24{in[7]}},in};endmodule

网址：https://hdlbits.01xz.net/wiki/Module_faddmodule top_module ( input [31:0] a, input [31:0] b, output [31:0] sum);//add16 add16_1( .a(a[15:0]), .b(b[15:0]), .sum(sum[15:0]), .cin(1'b0), .cout(c)); add16 add16_2( .a(a[31:16]), .b(b[31:16])

网址：https://hdlbits.01xz.net/wiki/Module_cseladdmodule top_module( input [31:0] a, input [31:0] b, output [31:0] sum); wire SW; reg [15:0] sum1;reg [15:0] sum2; add16 add16_1( //低16位，cin为0 .a(a[15:0]), .b(b[15:0]), .sum(sum[15:0]), .cout(S

网址：https://hdlbits.01xz.net/wiki/Module_addsubmodule top_module( input [31:0] a, input [31:0] b, input sub, output [31:0] sum); wire [31:0] b_change; assign b_change = b ^ {32{sub}}; wire cout;add16 add16_1(

网址：https://hdlbits.01xz.net/wiki/Always_casez// synthesis verilog_input_version verilog_2001module top_module ( input [7:0] in, output reg [2:0] pos ); always@(*) begin casez(in[7:0])

网址：https://hdlbits.01xz.net/wiki/Always_nolatches// synthesis verilog_input_version verilog_2001module top_module ( input [15:0] scancode, output reg left, output reg down, output reg right, output reg up ); always@(*)

网址：https://hdlbits.01xz.net/wiki/Vector100rmodule top_module( input [99:0] in, output reg [99:0] out); reg [99:0] i; always@(*) for (i = 0; i < 100; i = i + 1) begin out[i] = in[99-i];

网址：https://hdlbits.01xz.net/wiki/Popcount255module top_module( input [254:0] in, output [7:0] out ); reg [254:0] i; always@(*) begin out = 8'd0; for(i = 0;i <= 254;i = i + 1) begin