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RSS订阅转载 Python -- argparse usage
import argparseparser = argparse.ArgumentParser()parser.add_argument('--foo', help='foo help')args = parser.parse_args()add_help : Add a -h/–help option to the parser (default: True)Reference: ...
2019-07-05 16:20:01
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原创 functional coverage
Normally, functional coverage can be added in monitor and scoreboard.Adding it in monitor to cover transactionAdding it in socorboard to cover use case //coverage covergroup cov_a; a_...
2019-01-29 20:29:39
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原创 cm_hier file for Code Coverage
We can use -cm_hier to specify certain modules/instances to be included when VCS do compiling for coverage.Some useful cmd :+tree instance_name [level_number] : VCS compile only the specified insta...
2019-01-27 18:23:23
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转载 Siloti/KDB is what?
The Siloti™ Visibility Automation System transforms your verification methodology by eliminating the overhead associated with recording data for all the signals in a design. Unique automation technolo...
2019-01-08 20:09:53
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转载 X-prop
Why X-prop?Designers use RTL constructs to describe hardware behaviors. However, certain RTL simulation semantics are insufficient to accurately model the hardware behaviors. Therefore, simulation re...
2018-11-28 21:55:55
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转载 systemverilog $sformatf vs $sformat
The system function $sformatfbehaves like $sformat except that the string result is passed back as the function result value for $sformatf, not placed in the first argument as for $sformat.Some more ...
2018-11-20 22:23:33
11002
转载 `Timescale
In Verilog, all delays are governed by `timescale directive in the source file.-timescale=<time_unit/time_resolution>This is analysis time option. If present on the vlogan command line, it i...
2018-11-14 23:49:53
515
转载 Register Model -- Mirroring
The register model maintains a mirror of what it thinks the current value of registers is inside the DUT. The mirrored value is not guaranteed to be correct because the only information the register m...
2018-11-08 23:59:08
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转载 Overview of Register Model
A register model is typically composed of a hierarchy of blocks that map to the design hierarchy. Blocks can contain registers, register files and memories, as well as other blocks. The register layer...
2018-11-08 23:37:31
261
转载 Register Model Study -- Back-door read/write vs. peek/poke
You can perform back-door access to registers and memory by calling the following read/write methodswith their path argument as UVM_BACKDOOR:a) uvm_reg_field::read() or uvm_reg_field::write()b) uvm...
2018-11-08 18:28:15
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转载 $cast usage
The $cast system task can be used to assign values to variables that might not ordinarily be valid because of differing data type. $cast can be called as either a task or a function.The syntax for $c...
2018-11-08 15:12:40
169
原创 Tips: How to quit simulation by using UVM_ERROR
set_report_max_quit_count( 10 ); It will exit simulation after the number of UVM_ERRORS reaching 10.It can be added in build_phase or other phases. It can be added in base_test. If you add it in ...
2018-09-14 18:25:11
376
原创 Tips: Illegal rand variable type
Tips for vcs compileThe rand variable ‘half_period’ must be an integral type, an enum type, a packed struct, or of type ‘bit’. Change the type of the random variable ‘half_period’ to an integ...
2018-09-14 15:17:25
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转载 Strength length for scalar net signal values
Strength length for scalar net signal values
2018-09-14 14:40:02
273
转载 Real constants
Definition The real constant numbers shall be represented as described by IEEE Std 754-1985, an IEEE standard for double-precision floating-point numbers.Real numbers can be specified in either dec...
2018-09-14 14:11:12
443
转载 Level shifter
Level ShifterA level shifter in digital electronics, also called a logic-level shifter, is a circuit used to translate signals from one logic level or voltage domain to another, allowing compatibili...
2018-09-13 18:19:13
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