xilinx芯片管脚使用限制_FPGA__xilinx管脚说明.pdf

FPGA__xilinx管脚说明

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R Virtex™ 2.5 V

Field Programmable Gate Arrays

DS003-4 (v2.8) July 19, 2002 0 0 Production Product Specification

Virtex Pin Definitions

Table 1: Special Purpose Pins

Dedicated

Pin Name Pin Direction Description

GCK0, GCK1, Yes Input Clock input pins that connect to Global Clock Buffers. These pins become

GCK2, GCK3 user inputs when not needed for clocks.

M0, M1, M2 Yes Input Mode pins are used to specify the configuration mode.

CCLK Yes Input or The configuration Clock I/O pin: it is an input for SelectMAP and

Output slave-serial modes, and output in master-serial mode. After configuration,

it is input only, logic level = Don’t Care.

PROGRAM Yes Input Initiates a configuration sequence when asserted Low.

DONE Yes Bidirectional Indicates that configuration loading is complete, and that the start-up

sequence is in progress. The output can be open drain.

INIT No Bidirectional When Low, indicates that the configuration memory is being cleared. The

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