【iCore1S 双核心板_FPGA】例程五：Signal Tapll 实验——逻辑分析仪

最新推荐文章于 2022-12-03 14:32:39 发布

转载最新推荐文章于 2022-12-03 14:32:39 发布 · 178 阅读

本文介绍了一个基于Verilog HDL的信号灯控制器设计实现，通过使用12MHz时钟源来控制LED灯的亮灭周期，并且包含了复位逻辑、时钟信号发生器和LED状态控制模块等关键部分。

核心代码：

//--------------------Module_Signal_TapII-------------------//
module Signal_TapII(
    input CLK_12M,
    output FPGA_LEDR,
    output FPGA_LEDG,
    output FPGA_LEDB
    );
//--------------------------rst_n--------------------------//    
    reg [9:0]cnt_rst = 4'd0;
    reg rst_n = 1'd0;
    
    always @(posedge CLK_12M)
        begin
            if (cnt_rst == 4'd10)
                begin
                    rst_n <= 1'd1;
                    cnt_rst <= 4'd10;
                end
            else cnt_rst <= cnt_rst + 1'd1;
        end
        
//--------------------------led_clk--------------------------//    
    reg led_clk;
    reg [24:0]cnt_led;
    
    always @(posedge CLK_12M or negedge rst_n)
        if (!rst_n)
            begin
                led_clk <= 1'd0;
                cnt_led <= 25'd0;
            end
        else if(cnt_led == 25'd8000000)
            begin
                cnt_led <= 25'd0;
                led_clk <= ~led_clk;
            end
        else cnt_led <= cnt_led + 1'd1;
        
//---------------------------led---------------------------//            
    reg [2:0]led;
    
    always @(posedge led_clk or negedge rst_n)
        if (!rst_n)
            begin
                led <= 3'd1;
            end
        else
            begin
                if (led[2])
                    begin
                        led <= 3'd1;
                    end
                else 
                    begin
                        led <= led << 1'd1;
                    end
            end
    
    assign {FPGA_LEDR,FPGA_LEDG,FPGA_LEDB} = ~led;
//--------------------------endmodule-------------------------//        
endmodule