module Top_Clock (
output [6:0] T0,T1,T2,T3,T4,T5,T6,
input CP,_CR,EN
);
wire [7:0] hour,min,sec;
Divided_Frequency u0(Hz1,Hz500,Hz1000,_CR,CP);
counter60 u1(sec,_CR,EN,CP);
counter60 u2(min,_CR,EN,CP);
counter24 u3(hour,_CR,EN,CP);
TubeDecoder u4(T0,sec[3:0]);
TubeDecoder u5(T1,sec[7:4]);
TubeDecoder u6(T2,min[3:0]);
TubeDecoder u7(T3,min[7:4]);
TubeDecoder u8(T4,hour[3:0]);
TubeDecoder u9(T5,hour[7:4]);
endmodule;
module counter6 (Q,_CR,EN,CP);
input _CR,EN,CP;
output Q;
reg [3:0] Q;
always @ (posedge CP or negedge _CR)
begin
if(!_CR)
Q<=4'd0;
else if(!EN)
Q<=Q;
else if(Q==4'd5)
Q<=4'd0;
else Q<=Q+1'b1;
end
endmodule
module counter10 (Q,_CR,EN,CP);
input _CR,EN,CP;
output Q;
reg [3:0] Q;
always @ (posedge CP or negedge _CR)
begin
if(!_CR)
Q<=4'd0;
else if(!EN)
Q<=Q;
else if(Q==4'd9)
Q<=4'd0;
else Q<=Q+1'b1;
end
endmodule
module counter24 (Q, _CR, EN, CP);
input _CR, EN, CP;
output reg [7:0] Q;
always @(posedge CP or negedge _CR) begin
if (!_CR)
Q <= 8'd0;
else if (!EN)
Q <= Q;
else begin
if (Q[7:4] == 4'd2) begin // 十位为2
if (Q[3:0] == 4'd3) // 个位为3时归零
Q <= 8'd0;
else
Q[3:0] <= Q[3:0] + 1'b1;
end
else if (Q[3:0] == 4'd9) begin // 十位<2，个位为9时进位
Q[3:0] <= 4'd0;
Q[7:4] <= Q[7:4] + 1'b1;
end
else
Q[3:0] <= Q[3:0] + 1'b1;
end
end
endmodule
module counter60 (cnt,_CR,EN,CP);
input _CR,EN,CP;
output cnt;
reg [7:0] cnt;
wire en;
counter10 ones(cnt[3:0],_CR,EN,CP);
counter6 tens(cnt[7:4],_CR,en,CP);
assign en=(cnt[3:0]==4'd9);
endmodule
module TubeDecoder(
output reg[6:0]code,
input [3:0]number
);
always @(number)
begin
case(number)
4'd0:code<= 7'b000_0001;
4'd1:code<= 7'b100_1111;
4'd2:code<= 7'b001_0010;
4'd3:code<= 7'b000_0110;
4'd4:code<= 7'b100_1100;
4'd5:code<= 7'b010_0100;
4'd6:code<= 7'b010_0000;
4'd7:code<= 7'b000_1111;
4'd8:code<= 7'b000_0000;
4'd9:code<= 7'b000_0100;
4'ha:code<= 7'b000_1000;//show A
4'hb:code<= 7'b001_1000;//show P
default:code<= 7'b111 1111;
endcase
end
endmodule
module Divided_Frequency (Hz1,Hz500,Hz1000,_CR,CP);
output reg Hz1,Hz500,Hz1000;
input _CR,CP;
reg [31:0] cnt1=32'b0,cnt2=32'b0,cnt3=32'b0;
always @ (posedge CP or negedge _CR)//1000Hz
begin
if(!_CR)
begin
Hz1000<=1'b0;
cnt1<=1'b0;
end
else if(cnt1==32'd25000-1)
begin
Hz1000<=!Hz1000;
cnt1<=1'b0;
end
else cnt1<=cnt1+1'b0;
end
always @ (posedge CP or negedge _CR)//500Hz
begin
if(!_CR)
begin
Hz500<=1'b0;
cnt2<=1'b0;
end
else if(cnt2==32'd50000-1)
begin
Hz500<=!Hz500;
cnt2<=1'b0;
end
else cnt2<=cnt2+1'b0;
end
always @ (posedge CP or negedge _CR)//1Hz
begin
if(!_CR)
begin
Hz1<=1'b0;
cnt3<=1'b0;
end
else if(cnt3==32'd50000000-1)
begin
Hz1<=!Hz1;
cnt3<=1'b0;
end
else cnt3<=cnt3+1'b0;
end
endmodule
扫一扫
1352
被折叠的 条评论
为什么被折叠?
到【灌水乐园】发言
