c语言blackjack设计思路,Veriog——简易的BlackJack（21点）程序

- BlackJack(21点)游戏

BlackJack即我们所熟悉的21点游戏，这是一种扑克牌游戏。

玩这个游戏需要一副扑克牌。从2个花到10个花的牌值就是牌花的点数，而A的牌值可以为1或者11.

Verilog实现思路：

参考J.BHASKER的《Verilog HDL入门》，实现思路如下：

程序的输入包括牌值信号card_value，位宽为4，发牌准备信号card_rdy，以及时钟信号clock.

程序的输出包括获胜信号win，失败信号lost，以及准备好接收新牌信号request_card，这个信号的作用在于反馈回输入，牌值累加已经完成，可以发牌。

此外，内部处理需要当前状态信号bj_state，牌值总和信号total，位宽为5，牌值保存信号current_card_value，位宽为4，以及一个非常重要的A值的判别信号ace_as_11，其值为真是A作11，其值为假时，A作1.

采用状态机方式描绘这个程序，一共需要8个状态，分别为：

INITIAL_ST：初始状态，完成信号归零。

GETCARD_ST：接牌状态，card_rdy为高时，将牌值存储在内部信号内。

REMCARD_ST：将牌移走，进行运算。

ADD_ST：牌值累加，累加结果放在total信号内。

CHECK_ST：检查输赢状态。如果total信号值低于17，转入GETCARD_ST，再接收新牌；如果total信号值高于等于17，低于22，则判为赢，转入WIN_ST状态；否则进入BACKUP_ST状态，将A值置为1，再进行判断。

BACKUP_ST：这个状态中total值高于21，此时判断ace_as_11信号，其为高则total作减10处理，否则，判定为负。

LOST_ST： lost信号输出为高，并将程序置为准备好接收新牌，等待发牌准备完成信号。

WIN_ST： win信号输出为高，并将程序置为准备好接收新牌，等待发牌准备完成信号。

代码

`timescale 1ns/1ns

module blackjack(card_rdy,card_value,request_card,win,lost,clock);

input card_rdy,clock;

input [0:3] card_value;

output win,lost,request_card;

parameter INITIAL_ST = 0,GETCARD_ST = 1, REMCARD_ST = 2,ADD_ST = 3, CHECK_ST = 4,

WIN_ST = 5,BACKUP_ST = 6, LOST_ST = 7;

reg request_card,win,lost;

reg [0:2] bj_state;

reg [0:3] current_card_value;

reg [0:4] total;

reg ace_as_11;

always @(negedge clock)

case(bj_state)

INITIAL_ST:

begin

total <= 0;

ace_as_11 <= 0;

win <= 0;

lost <= 0;

bj_state <= GETCARD_ST;

end

GETCARD_ST:

begin

request_card <= 1;

if(card_rdy)

begin

current_card_value <= card_value;

bj_state <= REMCARD_ST;

end

end

REMCARD_ST:

if(card_rdy)

request_card <= 0;

else

bj_state <= ADD_ST;

ADD_ST:

begin

if(~ace_as_11 && current_card_value)

begin

current_card_value <= 11;

ace_as_11 <= 1;

end

total <= total + current_card_value;

bj_state <= CHECK_ST;

end

CHECK_ST:

if(total < 17)

bj_state <= GETCARD_ST;

else

begin

if(total < 22)

bj_state <= WIN_ST;

else

bj_state <= BACKUP_ST;

end

BACKUP_ST:

if(ace_as_11)

begin

total <= total - 10;

ace_as_11 <= 0;

bj_state <= CHECK_ST;

end

else

bj_state <= LOST_ST;

LOST_ST:

begin

lost <= 1;

request_card <= 1;

if(card_rdy)

bj_state <= INITIAL_ST;

end

WIN_ST:

begin

win <= 1;

request_card <= 1;

if(card_rdy)

bj_state <= INITIAL_ST;

end

default: bj_state <= INITIAL_ST;

endcase

endmodule

module blackjack_tb;

reg clock,card_rdy;

reg [0:3]card_value;

wire win,lost,request_card;

blackjack U1(.card_rdy(card_rdy),.clock(clock),.card_value(card_value),.win(win),.lost(lost),.request_card(request_card));

always #50 clock = !clock;

initial

begin

clock = 0;

card_rdy = 0;

card_value = 4'b0;

wait(request_card == 1)

begin

#50 card_rdy = 1;

card_value = 3;

#200 card_rdy =0;

end

wait(request_card == 1)

begin

#50 card_rdy = 1;

card_value = 4;

#200 card_rdy =0;

end

wait(request_card == 1)

begin

#50 card_rdy = 1;

card_value = 5;

#200 card_rdy =0;

end

wait(request_card == 1)

begin

#50 card_rdy = 1;

card_value = 1;

#200 card_rdy =0;

end

wait(request_card == 1)

begin

#50 card_rdy = 1;

card_value = 8;

#200 card_rdy =0;

end

end

endmodule