Cache Thrashing

博客介绍了代码中向量映射到关联缓存相同位置导致cache trashing的问题。由于不合理的向量对准,每次对向量元素的引用都会导致cache miss,性能变差。还给出两种防止方法,如改变向量维度,消除cache trashing可使循环加速至少100倍。

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考虑如下代码,三个大向量结合到第四个向量。

parameter max = 1024 * 1024
dimension a(max), b(max), c(max), d(max).
do i = 1, max
  a(i) = b(i) + c(i)d(i)
enddo

这四个向量逐个声明,因此他们在内存连续分配。每个向量都是 4MB 大小,102410244 bytes。因此这四个元素地址的低22位是相同的。向量映射到关联缓存的相同的位置。

为了执行某次计算,a(i), b(i), c(i), and d(i) 必须驻留在主存中,首先对 c(i), and d(i) 执行乘法。他们映射到缓存的相同位置,单两者可以同时驻留,因为缓存是2路组相联。在相同的地址位它可以容下2个cache line。为了执行加法,b(i) 需要在缓存中。它映射到缓存的相同位置,因此含c(i) 的cache line 挪出位置用于存放b(i),这里假设最近访问的是c(i)。为了存储结果到a(i),含d(i) 的 cache line 必须被替换。

现在,循环处理到了i+1迭代,含 c(i+1) 的cache line 必须重新载入cache,与因为有两个事实:

  1. c(i+1) 是一个不同于c(i) 的cache line,因此第一次它的 line 必须被载入
  2. c(i+1) 是一个相同于c(i)的cache line,但是已经被替换了在先前的迭代中,

相似的,cache line 含d(i+1) 的也同样需要被重新载入。事实上,每一个对一个向量元素的引用会导致一个cache miss,因为4个中只有两个需要的值可以同时驻留在cache中。尽管访问是一次一步的,没有cache line reuse。

这些行为称为 cache trashing,并且它导致非常差的性能。本质上减少了程序无缓存地使用内存。trashing 的原因是因为不合理的向量对准(vector alignment)。他们所有映射到相同的cache 位置。上面程序的对照是特别坏的因为 max 是非常大的会引起 trashing 在主存喻二级缓存。

使用 array padding 防止 trashing

两种方法防止 cache trashing

  1. 改变向量维度,使得其不再是 2 的平方。一个新的size将溢出内存,因此a(1),b(1),c(1),d(1) 将所有映射到不同的位置是理想的,比如 max = 1024*1024+32 将偏置每一个向量32个元素,或128bytes。这是一个 二级cache line 的大小。因此每个向量开始于一个不同的cache 地址。所有4个值可能同时驻留在cache,因此可能实现 cache line reuse。
  2. 对于2维向量。将主维改成奇数是有效的,如
dimension a(1024+1, 1024)

对于多维数组,改变两个甚至更多的维数:

dimension a(64+1, 64=1, 64)

消除cache trashing 使得循环加速至少100倍。

### STM32 H7 Cache Configuration and Usage #### Overview of Cache in STM32 H7 Series Microcontrollers In the STM32 H7 series microcontrollers, cache plays a crucial role in enhancing performance by reducing access times to frequently used data or instructions. The presence of both instruction (I-Cache) and data caches (D-Cache) significantly boosts efficiency when executing code from external memory devices like QSPI Flash or DDR SDRAM. The I-Cache is typically configured as an eight-way set associative with up to 32 KB capacity while D-Cache can be similarly sized but operates under different principles depending on whether write-through or write-back policies are applied[^1]. #### Configuring Caches Using CubeMX To configure these features via ST's graphical toolchain: - Open STM32CubeMX. - Select your target device within Project Manager tab after creating new project. - Navigate through System Core -> MPU/CPU settings where you will find options related specifically towards enabling/disabling Instruction/Data caching along side other parameters such as bufferability attributes which dictate how certain regions should interact with hardware buffers during read/write operations. For more advanced configurations beyond what’s offered directly inside this interface one may need direct register manipulation post-initialization phase using HAL libraries provided alongside documentation covering all available registers involved in controlling behavior around cached accesses versus non-cached ones based upon application requirements. ```c // Example Code Snippet for Enabling/Disabling Data & Instruction Caching Globally at Runtime HAL_EnableDCache(); HAL_DisableICache(); /* Or vice versa */ HAL_EnableICache(); HAL_DisableDCache(); ``` It must also be noted that proper setup involves careful consideration given not only toward size allocations per region defined earlier mentioned but ensuring coherency between multiple masters accessing shared resources simultaneously without causing conflicts leading potentially catastrophic failures due race conditions etc., especially important multi-core architectures found newer variants within family line-up. #### Common Issues and Solutions Related to Cache Utilization One common issue encountered might involve unexpected program flow alterations caused by stale copies residing inside local storage areas instead being fetched fresh each time requested externally – known colloquially amongst developers familiar territory simply referred 'cache thrashing'. To mitigate against occurrences similar natured events happening unexpectedly consider implementing strategies outlined below whenever applicable scenario presents itself naturally throughout development lifecycle stages ranging initial design phases until final deployment steps taken place later down road once everything has been thoroughly tested out beforehand properly. ##### Strategies to Prevent Cache Thrashing: - **Optimize Memory Access Patterns:** Ensure sequential reads/writes wherever possible since random patterns tend degrade overall throughput levels achieved over sustained periods operation. - **Use Non-cacheable Regions Wisely:** For critical sections requiring immediate updates reflect changes instantly across entire system scope define them explicitly outside influence reach normal hierarchical structures established otherwise default circumstances apply automatically behind scenes unbeknownst user intervention required whatsoever unless specified differently upfront intentionally so desired outcome reached successfully every single instance attempted thereafter consistently reliable fashion expected originally intended manner right off bat start go. - **Implement Software Prefetching Techniques Carefully:** While beneficial many scenarios involving complex algorithms processing large datasets efficiently enough meet stringent timing constraints imposed real-time applications domains caution advised prevent introducing unnecessary complexity could backfire worse than anticipated initially thought before embarking journey exploring potential optimizations paths forward moving ahead progressively step-by-step cautiously measured approach always recommended best practice guidelines followed closely adhere strictly maintain highest standards quality assurance measures implemented robustly safeguard long-term sustainability goals pursued relentlessly pursuit excellence maintained unwavering commitment never compromise integrity work produced delivered clients satisfaction guaranteed top priority utmost importance placed above anything else considered secondary matters irrelevant comparison contrast stark difference made clear understood fully comprehensive grasp subject matter discussed herein contained presented form coherent logical sequence easy follow understand absorb information conveyed effectively communicated clearly articulated precise terms avoiding ambiguity confusion arise misunderstandings occur minimized reduced lowest level feasible practical means available today modern era technology rapidly evolving landscape constantly changing shifting paradigms emerging trends shaping future directions heading towards tomorrow world awaits us thereupon lies endless possibilities opportunities await those willing brave challenges head-on embrace change open arms ready embark transformative journeys lead innovation breakthroughs unprecedented scales seen witnessed history books written about generations come remember fondly look back marvel achievements accomplished together united collective effort humanity striving achieve greater heights ever imagined dreamed possible previously confined limits boundaries constrained restricted outdated mindsets thinking processes obsolete replaced novel ideas concepts revolutionizing industries sectors transforming lives people everywhere planet Earth calls home sweet home indeed!
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