Verilog code

1、计数，用于对精度不高的计数

always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        div_cnt <= 1'd0;
    else
        div_cnt <= div_cnt + 1'b1;
end

assign  div_clk = div_cnt[8];       //div_cnt < 100

2、检测边沿

//--------------------------------
//Funtion : detect  start pos

always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        pos_arr <= 1'd0;
    else
        pos_arr <= {pos_arr[1:0] ,estart };
end

assign  start = pos_arr[1] & ~pos_arr[2]

 3、声明的不同最好在注释上面体现出来，而不是在变量名

//localparam        BAUD_END        =        5207            ;        //9600bps
localparam        BAUD_END        =        433                ;        //115200bps

4、组合数据，少使用了寄存器资源

always @(posedge clk_24m or negedge rst_n)
begin
    if(!rst_n)
        ov7670_data_out <= 1'd0;
    else if(cnt_byte == 1'b1)
        ov7670_data_out <= {ov7670_data_out[15:8] , ov7670_data};
    else 
        ov7670_data_out <= {ov7670_data , 8'd0};
end

 

。。。。待续

转载于:https://www.cnblogs.com/bixiaopengblog/p/7499098.html