2022.12.27---UART

本文介绍STM32微控制器中UART4模块的初始化配置及数据收发功能实现。通过具体的C语言代码示例,展示了如何设置引脚、波特率及寄存器等,实现了字符与字符串的发送和接收。

实现串口的数据收发

#include "uart4.h"


//uart4初始化
void hal_uart4_init()
{
	RCC->MP_AHB4ENSETR |= (0x1<<1);
	RCC->MP_AHB4ENSETR |= (0x1<<6);
	RCC->MP_APB1ENSETR |= (0x1<<16);
	//PB2设置为复用功能
	GPIOB->MODER &= (~(0X3<<4));
	GPIOB->MODER |= (0X2<<4);
	GPIOB->AFRL &= (~(0XF<<8));
	GPIOB->AFRL |= (0X8<<8);

	//PG11设置为复用功能
	GPIOG->MODER &= (~(0X3<<22));
	GPIOG->MODER |= (0X2<<22);
	GPIOG->AFRH &= (~(0XF<<12));
	GPIOG->AFRH |= (0X6<<12);

	//设置CR1
	USART4->CR1 &= (~(0x1 << 28));
	USART4->CR1 &= (~(0x1 << 12));
	USART4->CR1 &= (~(0x1 << 10));
	USART4->CR1 &= (~(0x1 << 15));
	
	//设置CR2
	USART4->CR2 &= (~(0x3 << 12));

	//设置PRESC
	USART4->PRESC &= (~(0xF << 0));

	//设置BRR
	USART4->BRR |= 0x22b;

	USART4->CR1 |= (0x1 << 3);
	USART4->CR1 |= (0x1 << 2);
	USART4->CR1 |= (0x1 << 0);
}

//发送一个字符
void put_char(const char ch)
{
	while(!(USART4->ISR & (0x1 << 7)));
	USART4->TDR = ch;
	while(!(USART4->ISR & (0x1 << 6)));
}

//发送一个字符串
void put_string(const char *str)
{
	while(*str)
	{
		put_char(*str++);
	}
	put_char('\n');
	put_char('\r');
}

//接收一个字符
char get_char()
{
	char ch=0;
	while(!(USART4->ISR & (0x1 << 5)));
	ch = USART4->RDR;//2.接收到数据
	return ch;
}

//接收一个字符串
char str[16]="";
char *get_string()
{
	int i=0;
	for(i=0;i<16;i++)
	{
		str[i] = get_char(); //接收一个字符
		put_char(str[i]); //发送一个字符 
		if(str[i] == '\r') //判断键盘enter键是否按下
			break;
	}
	str[i] = '\0';
	put_char('\n');
	return str;
}

Error-[IND] Identifier not declared /iccad/home/lvr/work/base_env/uart/dv/tests/tc_uart_test_case.sv, 54 Identifier 'tx_data' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none. Instance stack trace: $unit /edatools/synopsys/vcs/T-2022.06-SP2/etc/uvm-1.2/uvm_pkg.sv, 1 Error-[IND] Identifier not declared /iccad/home/lvr/work/base_env/uart/dv/tests/tc_uart_test_case.sv, 58 Identifier 'tx_data' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none. Instance stack trace: $unit /edatools/synopsys/vcs/T-2022.06-SP2/etc/uvm-1.2/uvm_pkg.sv, 1 Error-[MFNF] Member not found /iccad/home/lvr/work/base_env/uart/dv/tests/tc_uart_test_case.sv, 67 "this.read_word." Could not find member 'rdata' in class 'read_word_seq', at "/iccad/home/lvr/work/base_env/uart/dv/seq/apb_master_wr_sequence.sv", 44. Instance stack trace: $unit /edatools/synopsys/vcs/T-2022.06-SP2/etc/uvm-1.2/uvm_pkg.sv, 1 Error-[IND] Identifier not declared /iccad/home/lvr/work/base_env/uart/dv/tests/tc_uart_test_case.sv, 68 Identifier 'tx_data' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none. Instance stack trace: $unit /edatools/synopsys/vcs/T-2022.06-SP2/etc/uvm-1.2/uvm_pkg.sv, 1 Error-[IND] Identifier not declared /iccad/home/lvr/work/base_env/uart/dv/tests/tc_uart_test_case.sv, 55 Identifier 'tx_data' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none. Instance stack trace: $unit /edatools/synopsys/vcs/T-2022.06-SP2/etc/uvm-1.2/uvm_pkg.sv, 1 Error-[IND] Identifier not declared /iccad/home/lvr/work/base_env/uart/dv/tests/tc_uart_test_case.sv, 71 Identifier 'tx_data' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none. Instance stack trace: $unit /edatools/synopsys/vcs/T-2022.06-SP2/etc/uvm-1.2/uvm_pkg.sv, 1 报错了怎么改正
07-08
你遇到的错误是典型的 **SystemVerilog 编译器报错**,主要集中在以下几点: --- ### 🔍 错误分析 #### ✅ 1. `Identifier 'tx_data' has not been declared yet` - 表示变量 `tx_data` 没有在当前作用域中声明。 - 原因:你在使用 `tx_data` 前没有正确声明它。 #### ✅ 2. `Could not find member 'rdata' in class 'read_word_seq'` - 表示你尝试访问 `read_word.rdata`,但类 `read_word_seq` 中并没有定义这个字段。 --- ### ✅ 解决方案(逐条修复) --- #### 🔧 修复点 1:声明 `tx_data` 你之前写的是: ```systemverilog byte unsigned tx_data = 5'h12; ``` 但是 SystemVerilog 不允许对 `byte` 类型赋值一个位宽为 5 的常量。你需要改用 `logic [7:0]` 或者 `bit [7:0]` 并只使用低 5 位。 ✅ 修改为: ```systemverilog logic [7:0] tx_data; tx_data = 8'h12; // 只使用低5位 ``` --- #### 🔧 修复点 2:读取数据时 `rdata` 不存在 你写的代码: ```systemverilog read_data_act = read_word.rdata; ``` 如果你的 `read_word_seq` 类中没有定义 `rdata` 成员,则会报错。 🔍 确认你的 `read_word_seq` 类是否如下结构: ```systemverilog class read_word_seq extends uvm_sequence_item; rand bit [31:0] addr; bit [31:0] rdata; // 必须包含这个字段 // constructor and other methods... endclass ``` 如果没有,请添加: ✅ 添加 `rdata` 字段: ```systemverilog bit [31:0] rdata; ``` 否则你就不能使用 `read_word.rdata`。 --- ### ✅ 修改后的完整修复代码片段如下: ```systemverilog logic [7:0] tx_data; tx_data = 8'h12; // 发送的数据只使用低5位 `uvm_info("UART_TX", $sformatf("Sending 5-bit data: 0x%0x", tx_data[4:0]), UVM_LOW) // Step 3: 发送数据 `uvm_do_on_with(write_word, p_sequencer.bus_sqr, { addr == 32'h0000_0004; // 假设为发送 FIFO 地址 data == {24'd0, tx_data}; // 写入低8位 }) // Step 4: 接收并验证回环数据或外部返回数据 `uvm_do_on_with(read_word, p_sequencer.bus_sqr, { addr == 32'h0000_0008; // 假设为接收 FIFO 地址 }) read_data_act = read_word.rdata; if ((read_data_act[7:0]) == tx_data[4:0]) `uvm_info("UART_RX", $sformatf("Received expected data: 0x%x", read_data_act[7:0]), UVM_LOW) else `uvm_error("UART_RX", $sformatf("Received unexpected data: 0x%x != 0x%x", read_data_act[7:0], tx_data[4:0])) ``` --- ### ✅ 最终修正总结 | 错误 | 原因 | 修正方式 | |------|------|-----------| | `tx_data` 未声明 | 使用了不兼容类型赋值 | 改为 `logic [7:0] tx_data` 并赋值 `8'h12` | | `tx_data` 被当作 5bit 使用 | 没有显式截断 | 使用 `tx_data[4:0]` 显式提取低 5 位 | | `rdata` 找不到 | `read_word_seq` 没有该字段 | 在 `read_word_seq` 中添加 `bit [31:0] rdata` | --- ###
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