Quartus中仿真时出现no simulation input file assignment specify

最新推荐文章于 2022-03-16 20:28:05 发布
转载 最新推荐文章于 2022-03-16 20:28:05 发布 · 3.7k 阅读 · 9

分享一下我老师大神的人工智能教程！零基础，通俗易懂！http://blog.youkuaiyun.com/jiangjunshow

也欢迎大家转载本篇文章。分享知识，造福人民，实现我们中华民族伟大复兴！

               

最近学习FPGA，今天出现了一个错误提示：no simulation input file assignment specify ...以前没遇到过的

  具体过程是这样的，今天试验在各个工程文件中生成功能模块，然后新建一个工程，调用各个模块，导致进行仿真时提示了那个错误。然后百度了下，确实有些问题：

翻译成中文就是仿真文件没有被指定，要仿真的话先要建一个仿真文件: file -> new -> 选择Other file选项卡 -> Vector Waveform File 。  然后把输入输出端口加进去，再设置输入的信号，保存，就可以仿真了。

如果你之前已经建立过了，就打开assignments->settings->simulator settings

看里面的有个文本框 simulation input 里面是否为空，为空的话就要找到你所建立的Vector Waveform File 文件，是以*.VMF结尾的，如果没找到，你又以为你建立了Vector Waveform File ,很可能粗心的你还没保存Vector Waveform File ,保存了才会在project里面找到。

找到之后进行仿真，如果是functional simulation，要做processing>generate functional simulation netlist..不然会出现

Error: Run Generate Functional Simulation Netlist (quartus_map bmg_control --generate_functional_sim_netlist) to generate functional simulation netlist for top level entity bmg_control before running the Simulator (quartus_sim)之类的错误。最后在进行仿真，就可以看到波形图了。

           

给我老师的人工智能教程打call！http://blog.youkuaiyun.com/jiangjunshow
这里写图片描述
绿萝哥哥
关注
Quartus II简单仿真及no simulation input file错误解决方法
weixin_56646002的博客
09-05 9832
quartus II简单仿真及no simulation input file错误解决方法
Quartus ii 关于波形仿真
wsmslgdr的博客
04-23 1万+
一.点击File,点击new， 点击上图的蓝色部分，然后一直OK，出现如下界面 然后执行【File\Save As …】菜单命令，将其另存为add1a.vwf文件。采用执行【Edit/Insert/Insert Nodeor Bus】菜单命令，得到下图 点击红框部分，得到下图，对下图进行点击【Flier】下拉菜单选取【Pins:all】；点击【List】按钮显示找到的节点；点击【>>...
QUARTUS II 编译报错Error: Run Generate Functional Simulation Netlist的解决方案
06-19
QUARTUS II 编译报错Error: Run Generate Functional Simulation Netlist (...) to generate functional simulation netlist for top level entity bmg_control before running the Simulator (quartus_sim)的解决方案
Quartus中仿真时出现no simulation input file assignment specify 解决方法 (转载)
diaoguo3370的博客
09-22 2360
今天使用quartusII做了一下功能仿真，但是文件出现了问题 Error: Run Generate Functional Simulation Netlist (。。。) to generate functional simulation netlist for top level entity bmg_control before running the Simulator (...
Quartus II仿真出现问题Error: can‘t read “FileWatch(fileName)“: no such element in array
qq_51681487的博客
10-16 1万+
Determining the location of the ModelSim executable… Using: c:/intelfpga_lite/20.1/modelsim_ase/win32aloem/ To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executable
用Quartus仿真计数器模块：
EyreG97的博客
05-11 1万+
一：部分主体操作步骤：（省略顶层BDF文件及virlog文件过程及生成元件）1.观察计数器内部原理：2.创建vwf文件，添加node finder并仿真，观察波形和毛刺。3.使用signal tap 文件进行验证。二.0—9计数器中重点问题理解：（1）在①②，③④之间出现毛刺，因为OUT是几个子状态out[0][1][2][3]分别情况的组合，在输入端存在竞争，在输出端出现毛刺，即“冒险”。（2）...
Determining the location of the ModelSim executable... Using: D:\FPGA\modelsim\win64 To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Block1 -c Block1 --vector_source="D:/FPGA/Quartus/zuoye/Waveform.vwf" --testbench_file="D:/FPGA/Quartus/zuoye/simulation/qsim/Waveform.vwf.vt" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Sat Dec 20 17:21:44 2025 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Block1 -c Block1 --vector_source=D:/FPGA/Quartus/zuoye/Waveform.vwf --testbench_file=D:/FPGA/Quartus/zuoye/simulation/qsim/Waveform.vwf.vt Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Completed successfully. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="D:/FPGA/Quartus/zuoye/simulation/qsim/" Block1 -c Block1 Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Sat Dec 20 17:21:45 2025 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=D:/FPGA/Quartus/zuoye/simulation/qsim/ Block1 -c Block1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file Block1.vo in folder "D:/FPGA/Quartus/zuoye/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 4625 megabytes Info: Processing ended: Sat Dec 20 17:21:47 2025 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. **** Generating the ModelSim .do script **** D:/FPGA/Quartus/zuoye/simulation/qsim/Block1.do generated. Completed successfully. **** Running the ModelSim simulation **** D:/FPGA/modelsim/win64/vsim -c -do Block1.do Reading D:/FPGA/modelsim/tcl/vsim/pref.tcl # 10.4 # do Block1.do # ** Warning: (vlib-34) Library already exists at "work". # # Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014 # Start time: 17:21:48 on Dec 20,2025 # vlog -work work Block1.vo # -- Compiling module Block1 # -- Compiling module hard_block # # Top level modules: # Block1 # End time: 17:21:48 on Dec 20,2025, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014 # Start time: 17:21:48 on Dec 20,2025 # vlog -work work Waveform.vwf.vt # -- Compiling module Block1_vlg_vec_tst # # Top level modules: # Block1_vlg_vec_tst # End time: 17:21:48 on Dec 20,2025, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vsim -c -do "Block1.do" # Start time: 17:21:48 on Dec 20,2025 # ** Warning: (vsim-8891) All optimizations are turned off because the -novopt switch is in effect. This will cause your simulation to run very slowly. If you are using this switch to preserve visibility for Debug or PLI features please see the User's Manual section on Preserving Object Visibility with vopt. # # // ModelSim SE-64 10.4 Dec 3 2014 # // # // Copyright 1991-2014 Mentor Graphics Corporation # // All Rights Reserved. # // # // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION # // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS # // LICENSORS AND IS SUBJECT TO LICENSE TERMS. # // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL # // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM # // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. # // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER # // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. # // # Refreshing D:/FPGA/Quartus/zuoye/simulation/qsim/work.Block1_vlg_vec_tst # Loading work.Block1_vlg_vec_tst # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # Refreshing D:/FPGA/Quartus/zuoye/simulation/qsim/work.Block1 # Loading work.Block1 # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # Refreshing D:/FPGA/Quartus/zuoye/simulation/qsim/work.hard_block # Loading work.hard_block # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-3033) Block1.vo(76): Instantiation of 'cycloneive_io_obuf' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /Block1_vlg_vec_tst/i1 File: Block1.vo # Searched libraries: # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # D:/FPGA/Quartus/zuoye/simulation/qsim/work # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-3033) Block1.vo(89): Instantiation of 'cycloneive_io_ibuf' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /Block1_vlg_vec_tst/i1 File: Block1.vo # Searched libraries: # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # D:/FPGA/Quartus/zuoye/simulation/qsim/work # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-3033) Block1.vo(99): Instantiation of 'cycloneive_io_ibuf' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /Block1_vlg_vec_tst/i1 File: Block1.vo # Searched libraries: # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # D:/FPGA/Quartus/zuoye/simulation/qsim/work # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-3033) Block1.vo(109): Instantiation of 'cycloneive_io_ibuf' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /Block1_vlg_vec_tst/i1 File: Block1.vo # Searched libraries: # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # D:/FPGA/Quartus/zuoye/simulation/qsim/work # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-3033) Block1.vo(119): Instantiation of 'cycloneive_io_ibuf' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /Block1_vlg_vec_tst/i1 File: Block1.vo # Searched libraries: # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # D:/FPGA/Quartus/zuoye/simulation/qsim/work # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-3033) Block1.vo(129): Instantiation of 'cycloneive_lcell_comb' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /Block1_vlg_vec_tst/i1 File: Block1.vo # Searched libraries: # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # D:/FPGA/Quartus/zuoye/simulation/qsim/work # Error loading design Error loading design # End time: 17:21:50 on Dec 20,2025, Elapsed time: 0:00:02 # Errors: 90, Warnings: 1 Error.
最新发布
12-21
首先，用户的问题是关于解决... - 在Quartus中生成仿真文件时，选择“NativeLink”设置以自动映射库。 此方法基于Altera/Intel官方文档，能高效解决库访问和实例化错误。确保所有路径正确，避免路径中的中文或空格。
Determining the location of the ModelSim executable... Using: c:/intelfpga_lite/18.1/modelsim_ase/win32aloem/ To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jiantongdeng1 -c jiantongdeng1 --vector_source="C:/intelFPGA_lite/18.1/Waveform.vwf" --testbench_file="C:/intelFPGA_lite/18.1/simulation/qsim/Waveform.vwf.vt" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Tue Jul 01 16:50:48 2025 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jiantongdeng1 -c jiantongdeng1 --vector_source=C:/intelFPGA_lite/18.1/Waveform.vwf --testbench_file=C:/intelFPGA_lite/18.1/simulation/qsim/Waveform.vwf.vt Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Error (199014): Vector source file C:/intelFPGA_lite/18.1/Waveform.vwf specified with --testbench_vector_input_file option does not exist Error: Quartus Prime EDA Netlist Writer was unsuccessful. 1 error, 1 warning Error: Peak virtual memory: 4612 megabytes Error: Processing ended: Tue Jul 01 16:50:49 2025 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:01 Error.
07-02
在解决 ModelSim 与 Quartus 联合仿真过程中出现的 `Error (199014): Vector source file ... does not exist` 错误时，需要从多个方面排查问题根源。该错误通常表明仿真工具无法找到指定的测试平台文件（如 `...
Determining the location of the ModelSim executable... Using: D:\Quatus II 18.0\Quartus II 18.0\Quartus II 18.0\modelsim_ase\win32aloem To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off full_adder -c full_adder --vector_source="D:/Quatus II 18.0/pro/full_adder/Waveform.vwf" --testbench_file="D:/Quatus II 18.0/pro/full_adder/simulation/qsim/Waveform.vwf.vt" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Sun Sep 21 00:40:00 2025 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off full_adder -c full_adder --vector_source="D:/Quatus II 18.0/pro/full_adder/Waveform.vwf" --testbench_file="D:/Quatus II 18.0/pro/full_adder/simulation/qsim/Waveform.vwf.vt" Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Completed successfully. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="D:/Quatus II 18.0/pro/full_adder/simulation/qsim/" full_adder -c full_adder仿真一致卡在这里，如何解决
09-22
我们正在解决Quartus Prime 18.0生成功能仿真网表时卡在“仿真一致”步骤的问题。根据引用内容，用户提到了Quartus Prime 18.0的使用，包括RTL查看和仿真设置。但是，用户当前的问题是在生成功能仿真网表时卡在...
No&nbsp；simulation&nbsp；input&nbsp；file&nbsp；assignm…
芳
09-04 9579
QuartusII中仿真时出现No simulation input file assignment specified on simulator page of the settings dialog box解决方法   翻译成中文：仿真文件没有被指定，要仿真的话先要建一个仿真文件；  情况一：（你没有建过仿真文件）file -> new -> 选择Other file选项卡 -> Ve
关于使用QuartusII仿真时出现的错误
chen_baiyu的博客
05-02 1万+
使用QuartusII仿真时出现No simulation input file assignment specified on simulator page of the settings dialog box的解决方法 没有建立仿真文件。file->new->Vector Waveform File添加一个文件，写入输入输出端口，设置输入信号，保存并Add file to cur...
FPGA EDA
summer_and_autumn的博客
09-24 2584
波形仿真时发生No simulation input file assignment specified on simulator page of the Settings dialog box 意思是：在设置对话框的模拟器页上没有指定模拟输入文件分配 可能是没有添加wave文件 解决方案 ： 在
Quartus_FPGA遇到的问题
proton_boke的博客
11-25 5460
Quartus技术博客——软件使用
“No input file specified “问题的处理
LDR1109的博客
03-16 2392
接手新项目，配置的时候，遇上了“No input file specified”的问题，第一反应，是上网搜。 关于这个问题的帖子有很多，总的来说，得到的问题原因有： 一、跟路径有关系，路径没指对； 二、可能是权限的问题，如，不允许访问； 三、SCRIPT_FILENAME变量没有正确设置 我是 Win10 环境，线索呢，查看access.log的时候，发现返回的状态码是404；而错误日志的信息是“GetFileAttributesEx() "D:\web\html\chuanyi1\admin r.
quartus找不到硬件USB-blaster及驱动无法安装，解决方法
热门推荐
acccccccco的博客
03-16 1万+
quartus找不到硬件USB-blaster及驱动无法安装，解决方法 Windows无法安装USB-Blaster 解决办法： 1、进入，计算机–>>设备管理器。 2、找到设备USB-Blaster，此时是带有黄色感叹号的。 3、右键，更新驱动程序软件。 4、要选择“浏览计算机以查找驱动程序软件®”，如选择自动搜索是不能安装成功的，一定要手动搜索。 一般在安装的目录下搜索 注：Quartus II 安装完成后自带有USB-Blaster的驱动程序，因此不用再到网上去特意下载USB-Blast
QuartusII用自带波形文件做激励进行功能仿真
Studying……
02-25 1万+
主要步骤： 1.建立工程new->New project Wizard 2.输入verilog文件new->verilog hdl file 3.编译Processing->Start->Start Analyse & Synthesis 4.管脚分配Assiment->Pins在Location处双击，另外将不用的引脚设为高阻态 5.整体编译Start Compile 6.将仿真类型
关于Error: Can't compile duplicate declarations of entity "**" into library "work"的错误
weixin_30364325的博客
05-04 971
今天做SEG7模块添加74138时，出现了Error: Can't compile duplicate declarations of entity "**" into library "work"。“**”是我的一个模块文件名，这个文件名同时有一个.bdf文件，还有一个.v文件。 其中.bdf文件是我为了加74138时新建的文件，存盘时我没有改默认文件名，所以出现和...
quartusii仿真显示no simulation input file assignment specified on Simulator page of the Settings dialog box 是什么意思
05-29
在使用 Quartus II 进行仿真时，可能会遇到错误提示 `'No simulation input file assignment specified on Simulator page of the Settings dialog box'`。以下是该问题的原因分析及解决方法。 #### 错误原因 此...
评论
添加红包

请填写红包祝福语或标题

个

红包个数最小为10个

元

红包金额最低5元

当前余额3.43元 前往充值 >
需支付：10.00元
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付元
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明：

1.余额是钱包充值的虚拟货币，按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载，可以购买VIP、付费专栏及课程。

余额充值