arm CPS指令解释-优快云博客

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arm 官方手册对cps指令的解释：
The A32 and T32 instruction sets both include an instruction to manipulate PSTATE.{A, I, F} and PSTATE.M:

CPSIE {, #}
- Sets the specified PSTATE. {A, I, F} exception masks to 0, enabling the exception, and optionally changes to the specified mode.
CPSID {, #}
- Sets the specified PSTATE.{A, I, F} exception masks to 1, disabling the exception, and optionally changes to the specified mode.
CPS #
- Changes to the specified mode without affecting the PSTATE.{A, I, F} exception masks.

1 The Current Program Status Register, CPSR

Some PSTATE fields can be accessed using the Special-purpose Current Program Status Register (CPSR). The CPSR can be directly read using the MRS instruction, and directly written using the MSR (register) and MSR (immediate) instructions.
某些 PSTATE 字段可通过专用当前程序状态寄存器 (CPSR) 访问。可以使用 MRS 指令直接读取 CPSR，使用 MSR（寄存器）和 MSR（立即）指令直接写入 CPSR。
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1.1 N, Z, C, V, bits [31:28]

The PSTATE Condition flags.

1.2 Q, bit [27]

The PSTATE overflow or saturation flag.

1.3 SSBS, bit [23]

Speculative Store Bypass Safe (SSBS) bit, see Access permissions for instruction execution.

1.4 PAN, bit [22]

In Armv8.0, Reserved, RES0.
In Armv8.1, Privileged Access Never (PAN) state bit, see About the PAN bit

1.4.1 About the PAN bit

When the value of PSTATE.PAN is 1, any privileged data access from PL1 or EL2 to a virtual memory address that is accessible at EL0 generates a Permission fault.
当 PSTATE.PAN 的值为 1 时，从 PL1 或 EL2 对 EL0 可访问的虚拟内存地址进行的任何特权数据访问都会产生权限错误。
When the value of PSTATE.PAN is 0, the translation system is the same as in Armv8.0.
当 PSTATE.PAN 的值为 0 时，转换系统与 Armv8.0 相同。
A corresponding PAN bit is added to CPSR and SPSR for exception returns, and DSPSR for entry to and exit from Debug state.
为异常返回的 CPSR 和 SPSR 以及进入和退出调试状态的 DSPSR 添加了相应的 PAN 位。
A new SPAN bit is added to SCTLR that controls whether the PAN state bit is set on taking an exception to EL1 from either Secure or Non-secure state, or to EL3 from Secure state when EL3 is using AArch32.
SCTLR 中增加了一个新的 SPAN 位，用于控制从安全或非安全状态向 EL1 发送异常时是否设置 PAN 状态位，或在 EL3 使用 AArch32 时从安全状态向 EL3 发送异常时是否设置 PAN 状态位。
CPSR.PAN bit can be written using an MSR instruction at PL1 or higher. Data writes to CPSR.PAN using an MSR instruction at EL0 are ignored. The value that is returned for an MRS instruction of CPSR from EL0 is UNKNOWN. In keeping with all other writes to the CPSR, other than for instruction fetches, the effect of the PAN state bit does not need to be explicitly synchronized.
CPSR.PAN 位可使用 PL1 或更高版本的 MSR 指令写入。使用 EL0 的 MSR 指令写入 CPSR.PAN 的数据将被忽略。从 EL0 发送的 CPSR MRS 指令返回的值为未知。与所有其他对 CPSR 的写入（指令取回除外）一样，PAN 状态位的影响无需明确同步。

1.5 DIT, bit [21]

Shows the value of CPSR.DIT immediately before the exception was taken.

1.6 GE[3:0], bits [19:16]

The PSTATE greater than or equal flags.

1.7 E, bit [9]

The PSTATE endianness bit.

1.8 A, I, F, bits [8:6]

The PSTATE asynchronous exception mask bits.

1.9 M[4:0], bits [4:0]

The PSTATE mode bits.
PSTATE M模式位的含义见第三章，AArch32 state PE modes

2 CPS, CPSID, CPSIE指令

Change PE State changes one or more of the PSTATE.{A, I, F} interrupt mask bits and, optionally, the PSTATE.M mode field, without changing any other PSTATE bits.
更改 PE 状态可更改一个或多个 PSTATE.{A、I、F}中断屏蔽位，也可更改 PSTATE.M 模式字段，但不会更改任何其他 PSTATE 位。
CPS is treated as NOP if executed in User mode unless it is defined as being CONSTRAINED UNPREDICTABLE elsewhere in this section.
如果在用户模式下执行，CPS 将被视为 NOP，除非本节其他部分将其定义为 CONSTRAINED UNPRICTABLE。
The PE checks whether the value being written to PSTATE.M is legal. See Illegal changes to PSTATE.M.
PE 会检查写入 PSTATE.M 的值是否合法。请参阅对 PSTATE.M 的非法更改。

3 AArch32 state PE modes

Table G1-5 shows the PE modes defined by the Arm architecture, for execution in AArch32 state. In this table:

The PE mode column gives the name of each mode and the abbreviation used, for example, in the general-purpose register name suffixes used in AArch32 general-purpose registers, the PC, and the Special-purpose registers.
PE 模式列给出了每种模式的名称和缩写，例如在 AArch32 通用寄存器、PC 和专用寄存器中使用的通用寄存器名称后缀。
The Encoding column gives the corresponding PSTATE.M field.
编码栏给出了相应的 PSTATE.M 字段。
The Exception level column gives the Exception level at which the mode is implemented, including dependencies on the current Security state and on whether EL3 is using AArch32, see Exception levels.
Exception level（异常级别）列给出了执行该模式的异常级别，包括与当前安全状态和 EL3 是否使用 AArch32 的相关性，请参阅 Exception levels（异常级别）。