Verilog学习札记（1）：Structural models of combinational logic

Verilog所描述的I-O关系可以分为两类：

structural view: similar to creating a schematic

behavior view: could be a simple boolean equation model, a register transfer level (RTL) model or an algorithm

Verilog包含了26组预先定义好的组合逻辑门(no sequential primitive)，称为primitive，包括：

and, nand, or, nor, xor, xnor, buf, not...

利用primitive写half adder为例（structural view）：

module add_half (output c_out, sum, input a,b);

xor(sum,a,b); //output port of a primitive must be first in the list of ports!

and(c_out,a,b);

endmodule

attention: verilog is a case sensitive language

data type wire: used to establish connectivity in design, just as a physical wire establishes connectivity between gates

Actual ports and formal port: can be associated by position in port lists

这个方法在书上的example 4.2里用到，但是显然非常不方便，要将其一一对齐来写，所以在port lists的写法上有所改进，且不需要注意位置关系：

.formal_name(actual name)

formal_name: given in the declaration of the instantiated module

actual_name: used in the instantiation of the module

例如在写full adder时需要用到half adder:

Add_half M1  (.b(b),

.c_out(w2),

.a(a),

.sum(w1)

);