Vivado 一些常用tcl命令笔记_hw target-优快云博客

本文介绍了FPGA设计中的关键调试技巧，包括路径报告、资源使用报告、对象定位、网表导出、关闭调试会话、查看debug core及高扇出网络报告等。这些技巧对于优化FPGA设计和提高调试效率至关重要。

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report_timing 报告从一个cell到另一个cell之间路径

report_timing -from decode_stream_inst/slice_data_inst/cu_inst/mv_inst/scale_b/tb_reg[2] -to decode_stream_inst/slice_data_inst/cu_inst/mv_inst/scale_a/multadd_inst1/p_reg -name report_name

2. report_utilization 报告一个module的资源使用情况

report_utilization -cells sub_module_name

report_utilization -cells [get_cells sub_module_name]

3. show_objects 在schematic中定位一个object，

show_objects -name find_1 [get_cells "decode_stream_inst/slice_data_inst/cu_inst/mv_inst/scale_b/tb_reg[2]" ] 这样可以

show_objects -name find_1 [get_cells "decode_stream_inst/slice_data_inst/cu_inst/mv_inst/scale_b/tb_reg[2]/C" ] 这样不行

show_objects -name find_1 [get_nets -hierarchical -top_net_of_hierarchical_group "ivlOffset_temp_carry_n_0" ]

4. write_verilog 导出网表文件

write_verilog -mode design -force project_2.v

5. close_hw_target 关闭打开的debug session

get_hw_targets -filter { IS_OPENED == 1 }

返回结果 localhost:3121/xilinx_tcf/Digilent/210251A08870

close_hw_target localhost:3121/xilinx_tcf/Digilent/210251A08870

6. report_debug_core 查看当前设计中的debug_core

The best way to remove unwanted debug cores is: first use the "report_debug_core" tcl command to see if there are any cores in the design, then use the "delete_debug_core" command to remove them

7 报告fanout数，report_high_fanout_nets -fanout_greater_than 1 -max_nets 1000 -verbose

得到类似如下的表格

High Fan-out Nets Information

1. Summary

----------

+----------------------------------------------+--------+-------------+

| Net Name | Fanout | Driver Type |

+----------------------------------------------+--------+-------------+

| rst | 579 | PORT |

| slice_data_inst/cu_inst/y0_reg[3]_rep__0_n_0 | 385 | FDRE |

| slice_data_inst/cu_inst/y0_reg[3]_rep_n_0 | 385 | FDRE |

| slice_data_inst/cu_inst/y0_reg[3]_rep__1_n_0 | 384 | FDRE |