加减乘除
与或非、异或
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:09:07 06/12/2014
// Design Name:
// Module Name: t
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module t(
input wire [3:0] a,
input wire [3:0] b,
input wire [3:0] state,
output reg [7:0] result
);
reg [3:0] quotient;
integer j;
reg [3:0] remainder;
reg [3:0] saved_b;
always @(state)
case (state)
//add
8: result = a + b;
//sub
4: begin
result = (a > b) ? (a-b) : (b-a);
if (a < b)
result[7] = 1;
end
//multiple
2: result = a * b;
//div
1: begin
remainder = a;
saved_b = b;
quotient = 8'b00000000;
if (b == 0)
result = 8'b11111111;
else
begin
for (j = 0; j < 16; j = j+1)
if (remainder >= saved_b)
begin
remainder = remainder - saved_b;
quotient = quotient + 1;
end
result = remainder;
result[7] = quotient[3];
result[6] = quotient[2];
result[5] = quotient[1];
result[4] = quotient[0];
end
end
//and
12: result = a & b;
//or
6: result = a | b;
//not
3: begin
result = ~b;
result[7] = !a[3];
result[6] = !a[2];
result[5] = !a[1];
result[4] = !a[0];
end
//xor
9: result = a ^ b;
endcase
endmodule