Verilog HDL语言组合逻辑电路设计实列

内容

8位带进位端的加法器的设计

实现模块：

module adder_8(cout,sum,a,b,cin);
  input cin;
  input[7:0] a,b;
  output cout;
  output[7:0] sum;
  assign {cout,sum}=a+b+cin;
endmodule
  

测试模块：

`timescale 1ns/1ns
`include "adder_8.v"
module adder_8_test;
  reg cin;
  reg[7:0] a,b;
  wire cout;
  wire[7:0] sum;
  initial 
    begin
      cin=1;
      a=8'b0110;
      b=8'b0011;
     #100 cin=0;
               a=8'b100;
               b=8'b0110;
      #100 $stop;
    end
  adder_8 m(.cout(cout),.sum(sum),.a(a),.b(b),.cin(cin));
endmodule
      

指令译码电路设计

实现模块：

`define plus 3'd0
`define minus 3'd1
`define band 3'd2
`define bor 3'd3
`define unegate 3'd4
module alu(out,opcode,a,b);
  output[7:0] out;
  input[2:0] opcode;
  input[7:0] a,b;
  reg [7:0] out;
  always @(opcode or a or b)
    begin
      case(opcode)
        `plus:out=a+b;
        `minus:out=a-b;
        `band:out=a&b;
        `bor:out=a|b;
        `unegate:out=~a;
        default:out=8'hx;
      endcase
    end
endmodule

测试模块：

`timescale 1ns/1ns
`include "alu.v"
module alu_test;
  reg[7:0] a,b;
  reg[2:0] opcode;
  wire[7:0] out;
  initial
    begin
      a=4;
      b=6;
      opcode=3'd0;
      #100 opcode=3'd1;
      #100 opcode=3'd2;
      #100 opcode=3'd3;
      #100 opcode=3'd4;
      #100 $stop;
   end
  alu m(.out(out),.opcode(opcode),.a(a),.b(b));
endmodule;

比较重组信号设计

实现模块：

module sort4(ra,rb,rc,rd,a,b,c,d);
  parameter t=3;
  output[t:0] ra,rb,rc,rd;
  input[t:0] a,b,c,d;
  reg[t:0] ra,rb,rc,rd;
  always @(a or b or c or d)
  begin:local
    reg[t:0] va,vb,vc,vd;
    {va,vb,vc,vd}={a,b,c,d};
    sort2(va,vc);
    sort2(vb,vd);
    sort2(va,vb);
    sort2(vc,vd);
    sort2(vb,vc);
    {ra,rb,rc,rd}={va,vb,vc,vd};
  end
  task sort2;
    inout[t:0]x,y;
    reg [t:0]tmp;
    if(x>y)
      begin
        tmp=x;
        x=y;
        y=tmp;
      end
  endtask
endmodule

测试模块：

`timescale 1ns/1ns
`include "sort4.v"
module sort4_test;
  reg[3:0]a,b,c,d;
  wire[3:0] ra,rb,rc,rd;
  initial
    begin
      a=0;
      b=0;
      c=0;
      d=0;
      repeat(20)
        begin
          #100 a={$random}%15;
          b={$random}%15;
          c={$random}%15;
          d={$random}%15;
        end
        #100 $stop;
      end
  sort4 m(.ra(ra),.rb(rb),.rc(rc),.rd(rd),.a(a),.b(b),.c(c),.d(d));
endmodule

比较器设计

实现模块：

module compare(equal,a,b);
  parameter size=1;
  output equal;
  input[size-1:0] a,b;
  assign equal=(a==b)?1:0;
endmodule

测试模块：

`timescale 1ns/1ns
`include "compare.v"
module compare_test;
  reg a,b;
  wire equal;
  initial 
    begin
      a=0;
      b=0;
   repeat(10)
      begin
      #100 a={$random}%10;
               b={$random}%10;
     end
      #100 $stop;
     end
  compare m(.equal(equal),.a(a),.b(b));
endmodule

3-8译码器设计

实现模块：

module decoder(out,in);
  output[7:0] out;
  input[2:0] in;
  assign out=1'b1<<in;
endmodule

测试模块：

`timescale 1ns/1ns
`include "decoder.v"
module decoder_test;
 reg[2:0] in;
 wire[7:0] out;
 initial
  begin
   in=0;
   #100 in=3'b000;
   #100 in=3'b001;
   #100 in=3'b010;
   #100 in=3'b011;
  #100  in=3'b100;
    #100 in=3'b101;
    #100 in=3'b110;
    #100 in=3'b111;
  #100 $stop;
  end
 decoder m(.out(out),.in(in));
endmodule