写出下面代码用到的AT命令，讲解每个AT命令的具体的含义：
#include <base/functional/bind.h>
27 #include <base/functional/callback_forward.h>
28 #include <string.h>
29
30 #include "device/include/esco_parameters.h"
31 #include "hcidefs.h"
32 #include "hcimsgs.h"
33 #include "internal_include/bt_target.h"
34 #include "main/shim/acl_api.h"
35 #include "osi/include/allocator.h"
36 #include "stack/include/bt_dev_class.h"
37 #include "stack/include/bt_hdr.h"
38 #include "stack/include/bt_lap.h"
39 #include "stack/include/bt_octets.h"
40 #include "stack/include/bt_types.h"
41 #include "stack/include/btu_hcif.h"
42 #include "types/raw_address.h"
43
44 /* Message by message.... */
45
46 #define HCIC_PARAM_SIZE_INQUIRY 5
47
48 #define HCIC_INQ_INQ_LAP_OFF 0
49 #define HCIC_INQ_DUR_OFF 3
50 #define HCIC_INQ_RSP_CNT_OFF 4
51
52 /* Periodic Inquiry Mode */
53 #define HCIC_PARAM_SIZE_PER_INQ_MODE 9
54
55 #define HCI_PER_INQ_MAX_INTRVL_OFF 0
56 #define HCI_PER_INQ_MIN_INTRVL_OFF 2
57 #define HCI_PER_INQ_INQ_LAP_OFF 4
58 #define HCI_PER_INQ_DURATION_OFF 7
59 #define HCI_PER_INQ_RSP_CNT_OFF 8
60 /* Periodic Inquiry Mode */
61
62 /* Exit Periodic Inquiry Mode */
63 #define HCIC_PARAM_SIZE_EXIT_PER_INQ 0
64
65 /* Create Connection */
66 #define HCIC_PARAM_SIZE_CREATE_CONN 13
67
68 #define HCIC_CR_CONN_BD_ADDR_OFF 0
69 #define HCIC_CR_CONN_PKT_TYPES_OFF 6
70 #define HCIC_CR_CONN_REP_MODE_OFF 8
71 #define HCIC_CR_CONN_PAGE_SCAN_MODE_OFF 9
72 #define HCIC_CR_CONN_CLK_OFF_OFF 10
73 #define HCIC_CR_CONN_ALLOW_SWITCH_OFF 12
74 /* Create Connection */
75
76 /* Disconnect */
77 #define HCIC_PARAM_SIZE_DISCONNECT 3
78
79 #define HCI_DISC_HANDLE_OFF 0
80 #define HCI_DISC_REASON_OFF 2
81 /* Disconnect */
82
83 /* Add SCO Connection */
84 #define HCIC_PARAM_SIZE_ADD_SCO_CONN 4
85
86 #define HCI_ADD_SCO_HANDLE_OFF 0
87 #define HCI_ADD_SCO_PACKET_TYPES_OFF 2
88 /* Add SCO Connection */
89
90 /* Create Connection Cancel */
91 #define HCIC_PARAM_SIZE_CREATE_CONN_CANCEL 6
92
93 #define HCIC_CR_CONN_CANCEL_BD_ADDR_OFF 0
94 /* Create Connection Cancel */
95
96 /* Accept Connection Request */
97 #define HCIC_PARAM_SIZE_ACCEPT_CONN 7
98
99 #define HCI_ACC_CONN_BD_ADDR_OFF 0
100 #define HCI_ACC_CONN_ROLE_OFF 6
101 /* Accept Connection Request */
102
103 /* Reject Connection Request */
104 #define HCIC_PARAM_SIZE_REJECT_CONN 7
105
106 #define HCI_REJ_CONN_BD_ADDR_OFF 0
107 #define HCI_REJ_CONN_REASON_OFF 6
108 /* Reject Connection Request */
109
110 /* Link Key Request Reply */
111 #define HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY 22
112
113 #define HCI_LINK_KEY_REPLY_BD_ADDR_OFF 0
114 #define HCI_LINK_KEY_REPLY_LINK_KEY_OFF 6
115 /* Link Key Request Reply */
116
117 /* Link Key Request Neg Reply */
118 #define HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY 6
119
120 #define HCI_LINK_KEY_NEG_REP_BD_ADR_OFF 0
121 /* Link Key Request Neg Reply */
122
123 /* PIN Code Request Reply */
124 #define HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY 23
125
126 #define HCI_PIN_CODE_REPLY_BD_ADDR_OFF 0
127 #define HCI_PIN_CODE_REPLY_PIN_LEN_OFF 6
128 #define HCI_PIN_CODE_REPLY_PIN_CODE_OFF 7
129 /* PIN Code Request Reply */
130
131 /* Link Key Request Neg Reply */
132 #define HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY 6
133
134 #define HCI_PIN_CODE_NEG_REP_BD_ADR_OFF 0
135 /* Link Key Request Neg Reply */
136
137 /* Change Connection Type */
138 #define HCIC_PARAM_SIZE_CHANGE_CONN_TYPE 4
139
140 #define HCI_CHNG_PKT_TYPE_HANDLE_OFF 0
141 #define HCI_CHNG_PKT_TYPE_PKT_TYPE_OFF 2
142 /* Change Connection Type */
143
144 #define HCIC_PARAM_SIZE_CMD_HANDLE 2
145
146 #define HCI_CMD_HANDLE_HANDLE_OFF 0
147
148 /* Set Connection Encryption */
149 #define HCIC_PARAM_SIZE_SET_CONN_ENCRYPT 3
150
151 #define HCI_SET_ENCRYPT_HANDLE_OFF 0
152 #define HCI_SET_ENCRYPT_ENABLE_OFF 2
153 /* Set Connection Encryption */
154
155 /* Remote Name Request */
156 #define HCIC_PARAM_SIZE_RMT_NAME_REQ 10
157
158 #define HCI_RMT_NAME_BD_ADDR_OFF 0
159 #define HCI_RMT_NAME_REP_MODE_OFF 6
160 #define HCI_RMT_NAME_PAGE_SCAN_MODE_OFF 7
161 #define HCI_RMT_NAME_CLK_OFF_OFF 8
162 /* Remote Name Request */
163
164 /* Remote Name Request Cancel */
165 #define HCIC_PARAM_SIZE_RMT_NAME_REQ_CANCEL 6
166
167 #define HCI_RMT_NAME_CANCEL_BD_ADDR_OFF 0
168 /* Remote Name Request Cancel */
169
170 /* Remote Extended Features */
171 #define HCIC_PARAM_SIZE_RMT_EXT_FEATURES 3
172
173 #define HCI_RMT_EXT_FEATURES_HANDLE_OFF 0
174 #define HCI_RMT_EXT_FEATURES_PAGE_NUM_OFF 2
175 /* Remote Extended Features */
176
177 #define HCIC_PARAM_SIZE_SETUP_ESCO 17
178
179 #define HCI_SETUP_ESCO_HANDLE_OFF 0
180 #define HCI_SETUP_ESCO_TX_BW_OFF 2
181 #define HCI_SETUP_ESCO_RX_BW_OFF 6
182 #define HCI_SETUP_ESCO_MAX_LAT_OFF 10
183 #define HCI_SETUP_ESCO_VOICE_OFF 12
184 #define HCI_SETUP_ESCO_RETRAN_EFF_OFF 14
185 #define HCI_SETUP_ESCO_PKT_TYPES_OFF 15
186
187 #define HCIC_PARAM_SIZE_ACCEPT_ESCO 21
188
189 #define HCI_ACCEPT_ESCO_BDADDR_OFF 0
190 #define HCI_ACCEPT_ESCO_TX_BW_OFF 6
191 #define HCI_ACCEPT_ESCO_RX_BW_OFF 10
192 #define HCI_ACCEPT_ESCO_MAX_LAT_OFF 14
193 #define HCI_ACCEPT_ESCO_VOICE_OFF 16
194 #define HCI_ACCEPT_ESCO_RETRAN_EFF_OFF 18
195 #define HCI_ACCEPT_ESCO_PKT_TYPES_OFF 19
196
197 #define HCIC_PARAM_SIZE_REJECT_ESCO 7
198
199 #define HCI_REJECT_ESCO_BDADDR_OFF 0
200 #define HCI_REJECT_ESCO_REASON_OFF 6
201
202 /* Hold Mode */
203 #define HCIC_PARAM_SIZE_HOLD_MODE 6
204
205 #define HCI_HOLD_MODE_HANDLE_OFF 0
206 #define HCI_HOLD_MODE_MAX_PER_OFF 2
207 #define HCI_HOLD_MODE_MIN_PER_OFF 4
208 /* Hold Mode */
209
210 /* Sniff Mode */
211 #define HCIC_PARAM_SIZE_SNIFF_MODE 10
212
213 #define HCI_SNIFF_MODE_HANDLE_OFF 0
214 #define HCI_SNIFF_MODE_MAX_PER_OFF 2
215 #define HCI_SNIFF_MODE_MIN_PER_OFF 4
216 #define HCI_SNIFF_MODE_ATTEMPT_OFF 6
217 #define HCI_SNIFF_MODE_TIMEOUT_OFF 8
218 /* Sniff Mode */
219
220 /* Park Mode */
221 #define HCIC_PARAM_SIZE_PARK_MODE 6
222
223 #define HCI_PARK_MODE_HANDLE_OFF 0
224 #define HCI_PARK_MODE_MAX_PER_OFF 2
225 #define HCI_PARK_MODE_MIN_PER_OFF 4
226 /* Park Mode */
227
228 /* QoS Setup */
229 #define HCIC_PARAM_SIZE_QOS_SETUP 20
230
231 #define HCI_QOS_HANDLE_OFF 0
232 #define HCI_QOS_FLAGS_OFF 2
233 #define HCI_QOS_SERVICE_TYPE_OFF 3
234 #define HCI_QOS_TOKEN_RATE_OFF 4
235 #define HCI_QOS_PEAK_BANDWIDTH_OFF 8
236 #define HCI_QOS_LATENCY_OFF 12
237 #define HCI_QOS_DELAY_VAR_OFF 16
238 /* QoS Setup */
239
240 #define HCIC_PARAM_SIZE_SWITCH_ROLE 7
241
242 #define HCI_SWITCH_BD_ADDR_OFF 0
243 #define HCI_SWITCH_ROLE_OFF 6
244 /* Switch Role Request */
245
246 /* Write Policy Settings */
247 #define HCIC_PARAM_SIZE_WRITE_POLICY_SET 4
248
249 #define HCI_WRITE_POLICY_HANDLE_OFF 0
250 #define HCI_WRITE_POLICY_SETTINGS_OFF 2
251 /* Write Policy Settings */
252
253 /* Write Default Policy Settings */
254 #define HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET 2
255
256 #define HCI_WRITE_DEF_POLICY_SETTINGS_OFF 0
257 /* Write Default Policy Settings */
258
259 #define HCIC_PARAM_SIZE_SNIFF_SUB_RATE 8
260
261 #define HCI_SNIFF_SUB_RATE_HANDLE_OFF 0
262 #define HCI_SNIFF_SUB_RATE_MAX_LAT_OFF 2
263 #define HCI_SNIFF_SUB_RATE_MIN_REM_LAT_OFF 4
264 #define HCI_SNIFF_SUB_RATE_MIN_LOC_LAT_OFF 6
265 /* Sniff Subrating */
266
267 /* Extended Inquiry Response */
268 #define HCIC_PARAM_SIZE_EXT_INQ_RESP 241
269
270 #define HCIC_EXT_INQ_RESP_FEC_OFF 0
271 #define HCIC_EXT_INQ_RESP_RESPONSE 1
272 /* IO Capabilities Response */
273 #define HCIC_PARAM_SIZE_IO_CAP_RESP 9
274
275 #define HCI_IO_CAP_BD_ADDR_OFF 0
276 #define HCI_IO_CAPABILITY_OFF 6
277 #define HCI_IO_CAP_OOB_DATA_OFF 7
278 #define HCI_IO_CAP_AUTH_REQ_OFF 8
279
280 /* IO Capabilities Req Neg Reply */
281 #define HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY 7
282
283 #define HCI_IO_CAP_NR_BD_ADDR_OFF 0
284 #define HCI_IO_CAP_NR_ERR_CODE 6
285
286 /* Read Local OOB Data */
287 #define HCIC_PARAM_SIZE_R_LOCAL_OOB 0
288
289 /* Read Local OOB Extended Data */
290 #define HCIC_PARAM_SIZE_R_LOCAL_OOB_EXTENDED 0
291
292 #define HCIC_PARAM_SIZE_UCONF_REPLY 6
293
294 #define HCI_USER_CONF_BD_ADDR_OFF 0
295
296 #define HCIC_PARAM_SIZE_U_PKEY_REPLY 10
297
298 #define HCI_USER_PASSKEY_BD_ADDR_OFF 0
299 #define HCI_USER_PASSKEY_VALUE_OFF 6
300
301 #define HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY 6
302
303 #define HCI_USER_PASSKEY_NEG_BD_ADDR_OFF 0
304
305 /* Remote OOB Data Request Reply */
306 #define HCIC_PARAM_SIZE_REM_OOB_REPLY 38
307
308 #define HCI_REM_OOB_DATA_BD_ADDR_OFF 0
309 #define HCI_REM_OOB_DATA_C_OFF 6
310 #define HCI_REM_OOB_DATA_R_OFF 22
311
312 /* Remote OOB Data Request Negative Reply */
313 #define HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY 6
314
315 #define HCI_REM_OOB_DATA_NEG_BD_ADDR_OFF 0
316
317 /* Read Tx Power Level */
318 #define HCIC_PARAM_SIZE_R_TX_POWER 0
319
320 /* Read Default Erroneous Data Reporting */
321 #define HCIC_PARAM_SIZE_R_ERR_DATA_RPT 0
322
323 #define HCIC_PARAM_SIZE_SEND_KEYPRESS_NOTIF 7
324
325 #define HCI_SEND_KEYPRESS_NOTIF_BD_ADDR_OFF 0
326 #define HCI_SEND_KEYPRESS_NOTIF_NOTIF_OFF 6
327
328 /**** end of Simple Pairing Commands ****/
329
330 #define HCIC_PARAM_SIZE_SET_EVT_FILTER 9
331
332 #define HCI_FILT_COND_FILT_TYPE_OFF 0
333 #define HCI_FILT_COND_COND_TYPE_OFF 1
334 #define HCI_FILT_COND_FILT_OFF 2
335 /* Set Event Filter */
336
337 /* Delete Stored Key */
338 #define HCIC_PARAM_SIZE_DELETE_STORED_KEY 7
339
340 #define HCI_DELETE_KEY_BD_ADDR_OFF 0
341 #define HCI_DELETE_KEY_ALL_FLAG_OFF 6
342 /* Delete Stored Key */
343
344 /* Change Local Name */
345 #define HCIC_PARAM_SIZE_CHANGE_NAME BD_NAME_LEN
346
347 #define HCI_CHANGE_NAME_NAME_OFF 0
348 /* Change Local Name */
349
350 #define HCIC_PARAM_SIZE_READ_CMD 0
351
352 #define HCIC_PARAM_SIZE_WRITE_PARAM1 1
353
354 #define HCIC_WRITE_PARAM1_PARAM_OFF 0
355
356 #define HCIC_PARAM_SIZE_WRITE_PARAM2 2
357
358 #define HCIC_WRITE_PARAM2_PARAM_OFF 0
359
360 #define HCIC_PARAM_SIZE_WRITE_PARAM3 3
361
362 #define HCIC_WRITE_PARAM3_PARAM_OFF 0
363
364 #define HCIC_PARAM_SIZE_SET_AFH_CHANNELS 10
365
366 #define HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN 59
367 #define HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN 63
368
369 #define HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG 4
370
371 #define HCI_SCAN_CFG_INTERVAL_OFF 0
372 #define HCI_SCAN_CFG_WINDOW_OFF 2
373 /* Write Page Scan Activity */
374
375 /* Write Inquiry Scan Activity */
376 #define HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG 4
377
378 #define HCI_SCAN_CFG_INTERVAL_OFF 0
379 #define HCI_SCAN_CFG_WINDOW_OFF 2
380 /* Write Inquiry Scan Activity */
381
382 /* Host Controller to Host flow control */
383 #define HCI_HOST_FLOW_CTRL_OFF 0
384 #define HCI_HOST_FLOW_CTRL_ACL_ON 1
385 #define HCI_HOST_FLOW_CTRL_SCO_ON 2
386 #define HCI_HOST_FLOW_CTRL_BOTH_ON 3
387
388 #define HCIC_PARAM_SIZE_WRITE_AUTOMATIC_FLUSH_TIMEOUT 4
389
390 #define HCI_FLUSH_TOUT_HANDLE_OFF 0
391 #define HCI_FLUSH_TOUT_TOUT_OFF 2
392
393 #define HCIC_PARAM_SIZE_READ_TX_POWER 3
394
395 #define HCI_READ_TX_POWER_HANDLE_OFF 0
396 #define HCI_READ_TX_POWER_TYPE_OFF 2
397
398 /* Read transmit power level parameter */
399 #define HCI_READ_CURRENT 0x00
400 #define HCI_READ_MAXIMUM 0x01
401
402 #define HCIC_PARAM_SIZE_NUM_PKTS_DONE_SIZE sizeof(btmsg_hcic_num_pkts_done_t)
403
404 #define MAX_DATA_HANDLES 10
405
406 #define HCI_PKTS_DONE_NUM_HANDLES_OFF 0
407 #define HCI_PKTS_DONE_HANDLE_OFF 1
408 #define HCI_PKTS_DONE_NUM_PKTS_OFF 3
409
410 #define HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT 4
411
412 #define HCI_LINK_SUPER_TOUT_HANDLE_OFF 0
413 #define HCI_LINK_SUPER_TOUT_TOUT_OFF 2
414 /* Write Link Supervision Timeout */
415
416 #define MAX_IAC_LAPS 0x40
417
418 #define HCI_WRITE_IAC_LAP_NUM_OFF 0
419 #define HCI_WRITE_IAC_LAP_LAP_OFF 1
420 /* Write Current IAC LAP */
421
422 #define HCIC_PARAM_SIZE_CONFIGURE_DATA_PATH 3
423
424 /*******************************************************************************
425 * BLE Commands
426 * Note: "local_controller_id" is for transport, not counted in HCI
427 * message size
428 ******************************************************************************/
429 #define HCIC_BLE_RAND_DI_SIZE 8
430 #define HCIC_BLE_IRK_SIZE 16
431
432 #define HCIC_PARAM_SIZE_SET_USED_FEAT_CMD 8
433 #define HCIC_PARAM_SIZE_WRITE_RANDOM_ADDR_CMD 6
434 #define HCIC_PARAM_SIZE_BLE_WRITE_ADV_PARAMS 15
435 #define HCIC_PARAM_SIZE_BLE_WRITE_SCAN_RSP 31
436 #define HCIC_PARAM_SIZE_WRITE_ADV_ENABLE 1
437 #define HCIC_PARAM_SIZE_BLE_WRITE_SCAN_PARAM 7
438 #define HCIC_PARAM_SIZE_BLE_WRITE_SCAN_ENABLE 2
439 #define HCIC_PARAM_SIZE_BLE_CREATE_LL_CONN 25
440 #define HCIC_PARAM_SIZE_BLE_CREATE_CONN_CANCEL 0
441 #define HCIC_PARAM_SIZE_CLEAR_ACCEPTLIST 0
442 #define HCIC_PARAM_SIZE_ADD_ACCEPTLIST 7
443 #define HCIC_PARAM_SIZE_REMOVE_ACCEPTLIST 7
444 #define HCIC_PARAM_SIZE_BLE_UPD_LL_CONN_PARAMS 14
445 #define HCIC_PARAM_SIZE_SET_HOST_CHNL_CLASS 5
446 #define HCIC_PARAM_SIZE_READ_CHNL_MAP 2
447 #define HCIC_PARAM_SIZE_BLE_READ_REMOTE_FEAT 2
448 #define HCIC_PARAM_SIZE_BLE_ENCRYPT 32
449 #define HCIC_PARAM_SIZE_WRITE_LE_HOST_SUPPORTED 2
450
451 #define HCIC_BLE_RAND_DI_SIZE 8
452 #define HCIC_BLE_ENCRYPT_KEY_SIZE 16
453 #define HCIC_PARAM_SIZE_BLE_START_ENC \
454 (4 + HCIC_BLE_RAND_DI_SIZE + HCIC_BLE_ENCRYPT_KEY_SIZE)
455 #define HCIC_PARAM_SIZE_LTK_REQ_REPLY (2 + HCIC_BLE_ENCRYPT_KEY_SIZE)
456 #define HCIC_PARAM_SIZE_LTK_REQ_NEG_REPLY 2
457 #define HCIC_BLE_CHNL_MAP_SIZE 5
458 #define HCIC_PARAM_SIZE_BLE_WRITE_ADV_DATA 31
459
460 #define HCIC_PARAM_SIZE_BLE_ADD_DEV_RESOLVING_LIST (7 + HCIC_BLE_IRK_SIZE * 2)
461 #define HCIC_PARAM_SIZE_BLE_RM_DEV_RESOLVING_LIST 7
462 #define HCIC_PARAM_SIZE_BLE_SET_PRIVACY_MODE 8
463 #define HCIC_PARAM_SIZE_BLE_CLEAR_RESOLVING_LIST 0
464 #define HCIC_PARAM_SIZE_BLE_READ_RESOLVING_LIST_SIZE 0
465 #define HCIC_PARAM_SIZE_BLE_READ_RESOLVABLE_ADDR_PEER 7
466 #define HCIC_PARAM_SIZE_BLE_READ_RESOLVABLE_ADDR_LOCAL 7
467 #define HCIC_PARAM_SIZE_BLE_SET_ADDR_RESOLUTION_ENABLE 1
468 #define HCIC_PARAM_SIZE_BLE_SET_RAND_PRIV_ADDR_TIMOUT 2
469
470 #define HCIC_PARAM_SIZE_BLE_READ_PHY 2
471 #define HCIC_PARAM_SIZE_BLE_SET_DEFAULT_PHY 3
472 #define HCIC_PARAM_SIZE_BLE_SET_PHY 7
473 #define HCIC_PARAM_SIZE_BLE_ENH_RX_TEST 3
474 #define HCIC_PARAM_SIZE_BLE_ENH_TX_TEST 4
475
476 #define HCIC_PARAM_SIZE_BLE_SET_DATA_LENGTH 6
477 #define HCIC_PARAM_SIZE_BLE_WRITE_EXTENDED_SCAN_PARAM 11
478
479 #define HCIC_PARAM_SIZE_BLE_RC_PARAM_REQ_REPLY 14
480 #define HCIC_PARAM_SIZE_BLE_RC_PARAM_REQ_NEG_REPLY 3
481
482 static void btsnd_hcic_disconnect(uint16_t handle, uint8_t reason) {
483 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
484 uint8_t* pp = (uint8_t*)(p + 1);
485
486 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_DISCONNECT;
487 p->offset = 0;
488
489 UINT16_TO_STREAM(pp, HCI_DISCONNECT);
490 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_DISCONNECT);
491 UINT16_TO_STREAM(pp, handle);
492 UINT8_TO_STREAM(pp, reason);
493
494 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
495 }
496
497 void btsnd_hcic_add_SCO_conn(uint16_t handle, uint16_t packet_types) {
498 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
499 uint8_t* pp = (uint8_t*)(p + 1);
500
501 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ADD_SCO_CONN;
502 p->offset = 0;
503
504 UINT16_TO_STREAM(pp, HCI_ADD_SCO_CONNECTION);
505 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ADD_SCO_CONN);
506
507 UINT16_TO_STREAM(pp, handle);
508 UINT16_TO_STREAM(pp, packet_types);
509
510 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
511 }
512
513 void btsnd_hcic_create_conn_cancel(const RawAddress& dest) {
514 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
515 uint8_t* pp = (uint8_t*)(p + 1);
516
517 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CREATE_CONN_CANCEL;
518 p->offset = 0;
519
520 UINT16_TO_STREAM(pp, HCI_CREATE_CONNECTION_CANCEL);
521 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CREATE_CONN_CANCEL);
522
523 BDADDR_TO_STREAM(pp, dest);
524
525 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
526 }
527
528 void btsnd_hcic_accept_conn(const RawAddress& dest, uint8_t role) {
529 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
530 uint8_t* pp = (uint8_t*)(p + 1);
531
532 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ACCEPT_CONN;
533 p->offset = 0;
534
535 UINT16_TO_STREAM(pp, HCI_ACCEPT_CONNECTION_REQUEST);
536 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ACCEPT_CONN);
537 BDADDR_TO_STREAM(pp, dest);
538 UINT8_TO_STREAM(pp, role);
539
540 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
541 }
542
543 void btsnd_hcic_reject_conn(const RawAddress& dest, uint8_t reason) {
544 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
545 uint8_t* pp = (uint8_t*)(p + 1);
546
547 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REJECT_CONN;
548 p->offset = 0;
549
550 UINT16_TO_STREAM(pp, HCI_REJECT_CONNECTION_REQUEST);
551 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REJECT_CONN);
552
553 BDADDR_TO_STREAM(pp, dest);
554 UINT8_TO_STREAM(pp, reason);
555
556 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
557 }
558
559 void btsnd_hcic_link_key_req_reply(const RawAddress& bd_addr,
560 const LinkKey& link_key) {
561 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
562 uint8_t* pp = (uint8_t*)(p + 1);
563
564 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY;
565 p->offset = 0;
566
567 UINT16_TO_STREAM(pp, HCI_LINK_KEY_REQUEST_REPLY);
568 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY);
569
570 BDADDR_TO_STREAM(pp, bd_addr);
571 ARRAY16_TO_STREAM(pp, link_key.data());
572
573 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
574 }
575
576 void btsnd_hcic_link_key_neg_reply(const RawAddress& bd_addr) {
577 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
578 uint8_t* pp = (uint8_t*)(p + 1);
579
580 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY;
581 p->offset = 0;
582
583 UINT16_TO_STREAM(pp, HCI_LINK_KEY_REQUEST_NEG_REPLY);
584 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY);
585
586 BDADDR_TO_STREAM(pp, bd_addr);
587
588 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
589 }
590
591 void btsnd_hcic_pin_code_req_reply(const RawAddress& bd_addr,
592 uint8_t pin_code_len, PIN_CODE pin_code) {
593 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
594 uint8_t* pp = (uint8_t*)(p + 1);
595 int i;
596
597 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY;
598 p->offset = 0;
599
600 UINT16_TO_STREAM(pp, HCI_PIN_CODE_REQUEST_REPLY);
601 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY);
602
603 BDADDR_TO_STREAM(pp, bd_addr);
604 UINT8_TO_STREAM(pp, pin_code_len);
605
606 for (i = 0; i < pin_code_len; i++) *pp++ = *pin_code++;
607
608 for (; i < PIN_CODE_LEN; i++) *pp++ = 0;
609
610 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
611 }
612
613 void btsnd_hcic_pin_code_neg_reply(const RawAddress& bd_addr) {
614 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
615 uint8_t* pp = (uint8_t*)(p + 1);
616
617 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY;
618 p->offset = 0;
619
620 UINT16_TO_STREAM(pp, HCI_PIN_CODE_REQUEST_NEG_REPLY);
621 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY);
622
623 BDADDR_TO_STREAM(pp, bd_addr);
624
625 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
626 }
627
628 void btsnd_hcic_change_conn_type(uint16_t handle, uint16_t packet_types) {
629 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
630 uint8_t* pp = (uint8_t*)(p + 1);
631
632 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_CONN_TYPE;
633 p->offset = 0;
634
635 UINT16_TO_STREAM(pp, HCI_CHANGE_CONN_PACKET_TYPE);
636 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CHANGE_CONN_TYPE);
637
638 UINT16_TO_STREAM(pp, handle);
639 UINT16_TO_STREAM(pp, packet_types);
640
641 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
642 }
643
644 void btsnd_hcic_auth_request(uint16_t handle) {
645 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
646 uint8_t* pp = (uint8_t*)(p + 1);
647
648 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
649 p->offset = 0;
650
651 UINT16_TO_STREAM(pp, HCI_AUTHENTICATION_REQUESTED);
652 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
653
654 UINT16_TO_STREAM(pp, handle);
655
656 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
657 }
658
659 void btsnd_hcic_set_conn_encrypt(uint16_t handle, bool enable) {
660 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
661 uint8_t* pp = (uint8_t*)(p + 1);
662
663 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SET_CONN_ENCRYPT;
664 p->offset = 0;
665
666 UINT16_TO_STREAM(pp, HCI_SET_CONN_ENCRYPTION);
667 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SET_CONN_ENCRYPT);
668
669 UINT16_TO_STREAM(pp, handle);
670 UINT8_TO_STREAM(pp, enable);
671
672 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
673 }
674
675 void btsnd_hcic_rmt_ext_features(uint16_t handle, uint8_t page_num) {
676 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
677 uint8_t* pp = (uint8_t*)(p + 1);
678
679 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_RMT_EXT_FEATURES;
680 p->offset = 0;
681
682 UINT16_TO_STREAM(pp, HCI_READ_RMT_EXT_FEATURES);
683 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_RMT_EXT_FEATURES);
684
685 UINT16_TO_STREAM(pp, handle);
686 UINT8_TO_STREAM(pp, page_num);
687
688 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
689 }
690
691 void btsnd_hcic_rmt_ver_req(uint16_t handle) {
692 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
693 uint8_t* pp = (uint8_t*)(p + 1);
694
695 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
696 p->offset = 0;
697
698 UINT16_TO_STREAM(pp, HCI_READ_RMT_VERSION_INFO);
699 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
700
701 UINT16_TO_STREAM(pp, handle);
702
703 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
704 }
705
706 void btsnd_hcic_read_rmt_clk_offset(uint16_t handle) {
707 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
708 uint8_t* pp = (uint8_t*)(p + 1);
709
710 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
711 p->offset = 0;
712
713 UINT16_TO_STREAM(pp, HCI_READ_RMT_CLOCK_OFFSET);
714 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
715
716 UINT16_TO_STREAM(pp, handle);
717
718 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
719 }
720
721 void btsnd_hcic_setup_esco_conn(uint16_t handle, uint32_t transmit_bandwidth,
722 uint32_t receive_bandwidth,
723 uint16_t max_latency, uint16_t voice,
724 uint8_t retrans_effort, uint16_t packet_types) {
725 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
726 uint8_t* pp = (uint8_t*)(p + 1);
727
728 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SETUP_ESCO;
729 p->offset = 0;
730
731 UINT16_TO_STREAM(pp, HCI_SETUP_ESCO_CONNECTION);
732 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SETUP_ESCO);
733
734 UINT16_TO_STREAM(pp, handle);
735 UINT32_TO_STREAM(pp, transmit_bandwidth);
736 UINT32_TO_STREAM(pp, receive_bandwidth);
737 UINT16_TO_STREAM(pp, max_latency);
738 UINT16_TO_STREAM(pp, voice);
739 UINT8_TO_STREAM(pp, retrans_effort);
740 UINT16_TO_STREAM(pp, packet_types);
741
742 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
743 }
744
745 void btsnd_hcic_accept_esco_conn(const RawAddress& bd_addr,
746 uint32_t transmit_bandwidth,
747 uint32_t receive_bandwidth,
748 uint16_t max_latency, uint16_t content_fmt,
749 uint8_t retrans_effort,
750 uint16_t packet_types) {
751 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
752 uint8_t* pp = (uint8_t*)(p + 1);
753
754 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ACCEPT_ESCO;
755 p->offset = 0;
756
757 UINT16_TO_STREAM(pp, HCI_ACCEPT_ESCO_CONNECTION);
758 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ACCEPT_ESCO);
759
760 BDADDR_TO_STREAM(pp, bd_addr);
761 UINT32_TO_STREAM(pp, transmit_bandwidth);
762 UINT32_TO_STREAM(pp, receive_bandwidth);
763 UINT16_TO_STREAM(pp, max_latency);
764 UINT16_TO_STREAM(pp, content_fmt);
765 UINT8_TO_STREAM(pp, retrans_effort);
766 UINT16_TO_STREAM(pp, packet_types);
767
768 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
769 }
770
771 void btsnd_hcic_reject_esco_conn(const RawAddress& bd_addr, uint8_t reason) {
772 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
773 uint8_t* pp = (uint8_t*)(p + 1);
774
775 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REJECT_ESCO;
776 p->offset = 0;
777
778 UINT16_TO_STREAM(pp, HCI_REJECT_ESCO_CONNECTION);
779 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REJECT_ESCO);
780
781 BDADDR_TO_STREAM(pp, bd_addr);
782 UINT8_TO_STREAM(pp, reason);
783
784 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
785 }
786
787 void btsnd_hcic_hold_mode(uint16_t handle, uint16_t max_hold_period,
788 uint16_t min_hold_period) {
789 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
790 uint8_t* pp = (uint8_t*)(p + 1);
791
792 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_HOLD_MODE;
793 p->offset = 0;
794
795 UINT16_TO_STREAM(pp, HCI_HOLD_MODE);
796 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_HOLD_MODE);
797
798 UINT16_TO_STREAM(pp, handle);
799 UINT16_TO_STREAM(pp, max_hold_period);
800 UINT16_TO_STREAM(pp, min_hold_period);
801
802 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
803 }
804
805 void btsnd_hcic_sniff_mode(uint16_t handle, uint16_t max_sniff_period,
806 uint16_t min_sniff_period, uint16_t sniff_attempt,
807 uint16_t sniff_timeout) {
808 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
809 uint8_t* pp = (uint8_t*)(p + 1);
810
811 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SNIFF_MODE;
812 p->offset = 0;
813
814 UINT16_TO_STREAM(pp, HCI_SNIFF_MODE);
815 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SNIFF_MODE);
816
817 UINT16_TO_STREAM(pp, handle);
818 UINT16_TO_STREAM(pp, max_sniff_period);
819 UINT16_TO_STREAM(pp, min_sniff_period);
820 UINT16_TO_STREAM(pp, sniff_attempt);
821 UINT16_TO_STREAM(pp, sniff_timeout);
822
823 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
824 }
825
826 void btsnd_hcic_exit_sniff_mode(uint16_t handle) {
827 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
828 uint8_t* pp = (uint8_t*)(p + 1);
829
830 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
831 p->offset = 0;
832
833 UINT16_TO_STREAM(pp, HCI_EXIT_SNIFF_MODE);
834 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
835
836 UINT16_TO_STREAM(pp, handle);
837
838 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
839 }
840
841 void btsnd_hcic_park_mode(uint16_t handle, uint16_t beacon_max_interval,
842 uint16_t beacon_min_interval) {
843 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
844 uint8_t* pp = (uint8_t*)(p + 1);
845
846 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PARK_MODE;
847 p->offset = 0;
848
849 UINT16_TO_STREAM(pp, HCI_PARK_MODE);
850 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PARK_MODE);
851
852 UINT16_TO_STREAM(pp, handle);
853 UINT16_TO_STREAM(pp, beacon_max_interval);
854 UINT16_TO_STREAM(pp, beacon_min_interval);
855
856 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
857 }
858
859 void btsnd_hcic_exit_park_mode(uint16_t handle) {
860 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
861 uint8_t* pp = (uint8_t*)(p + 1);
862
863 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
864 p->offset = 0;
865
866 UINT16_TO_STREAM(pp, HCI_EXIT_PARK_MODE);
867 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
868
869 UINT16_TO_STREAM(pp, handle);
870
871 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
872 }
873
874 static void btsnd_hcic_switch_role(const RawAddress& bd_addr, uint8_t role) {
875 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
876 uint8_t* pp = (uint8_t*)(p + 1);
877
878 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SWITCH_ROLE;
879 p->offset = 0;
880
881 UINT16_TO_STREAM(pp, HCI_SWITCH_ROLE);
882 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SWITCH_ROLE);
883
884 BDADDR_TO_STREAM(pp, bd_addr);
885 UINT8_TO_STREAM(pp, role);
886
887 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
888 }
889
890 void btsnd_hcic_write_policy_set(uint16_t handle, uint16_t settings) {
891 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
892 uint8_t* pp = (uint8_t*)(p + 1);
893
894 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_POLICY_SET;
895 p->offset = 0;
896 UINT16_TO_STREAM(pp, HCI_WRITE_POLICY_SETTINGS);
897 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_POLICY_SET);
898
899 UINT16_TO_STREAM(pp, handle);
900 UINT16_TO_STREAM(pp, settings);
901
902 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
903 }
904
905 void btsnd_hcic_write_def_policy_set(uint16_t settings) {
906 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
907 uint8_t* pp = (uint8_t*)(p + 1);
908
909 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET;
910 p->offset = 0;
911 UINT16_TO_STREAM(pp, HCI_WRITE_DEF_POLICY_SETTINGS);
912 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET);
913
914 UINT16_TO_STREAM(pp, settings);
915
916 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
917 }
918
919 void btsnd_hcic_set_event_filter(uint8_t filt_type, uint8_t filt_cond_type,
920 uint8_t* filt_cond, uint8_t filt_cond_len) {
921 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
922 uint8_t* pp = (uint8_t*)(p + 1);
923
924 p->offset = 0;
925
926 UINT16_TO_STREAM(pp, HCI_SET_EVENT_FILTER);
927
928 if (filt_type) {
929 p->len = (uint16_t)(HCIC_PREAMBLE_SIZE + 2 + filt_cond_len);
930 UINT8_TO_STREAM(pp, (uint8_t)(2 + filt_cond_len));
931
932 UINT8_TO_STREAM(pp, filt_type);
933 UINT8_TO_STREAM(pp, filt_cond_type);
934
935 if (filt_cond_type == HCI_FILTER_COND_DEVICE_CLASS) {
936 DEVCLASS_TO_STREAM(pp, filt_cond);
937 filt_cond += kDevClassLength;
938 DEVCLASS_TO_STREAM(pp, filt_cond);
939 filt_cond += kDevClassLength;
940
941 filt_cond_len -= (2 * kDevClassLength);
942 } else if (filt_cond_type == HCI_FILTER_COND_BD_ADDR) {
943 BDADDR_TO_STREAM(pp, *((RawAddress*)filt_cond));
944 filt_cond += BD_ADDR_LEN;
945
946 filt_cond_len -= BD_ADDR_LEN;
947 }
948
949 if (filt_cond_len) ARRAY_TO_STREAM(pp, filt_cond, filt_cond_len);
950 } else {
951 p->len = (uint16_t)(HCIC_PREAMBLE_SIZE + 1);
952 UINT8_TO_STREAM(pp, 1);
953
954 UINT8_TO_STREAM(pp, filt_type);
955 }
956
957 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
958 }
959
960 void btsnd_hcic_write_pin_type(uint8_t type) {
961 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
962 uint8_t* pp = (uint8_t*)(p + 1);
963
964 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
965 p->offset = 0;
966
967 UINT16_TO_STREAM(pp, HCI_WRITE_PIN_TYPE);
968 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
969
970 UINT8_TO_STREAM(pp, type);
971
972 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
973 }
974
975 void btsnd_hcic_delete_stored_key(const RawAddress& bd_addr,
976 bool delete_all_flag) {
977 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
978 uint8_t* pp = (uint8_t*)(p + 1);
979
980 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_DELETE_STORED_KEY;
981 p->offset = 0;
982
983 UINT16_TO_STREAM(pp, HCI_DELETE_STORED_LINK_KEY);
984 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_DELETE_STORED_KEY);
985
986 BDADDR_TO_STREAM(pp, bd_addr);
987 UINT8_TO_STREAM(pp, delete_all_flag);
988
989 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
990 }
991
992 void btsnd_hcic_change_name(BD_NAME name) {
993 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
994 uint8_t* pp = (uint8_t*)(p + 1);
995 uint16_t len = strlen((char*)name) + 1;
996
997 memset(pp, 0, HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_NAME);
998
999 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_NAME;
1000 p->offset = 0;
1001
1002 UINT16_TO_STREAM(pp, HCI_CHANGE_LOCAL_NAME);
1003 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CHANGE_NAME);
1004
1005 if (len > HCIC_PARAM_SIZE_CHANGE_NAME) len = HCIC_PARAM_SIZE_CHANGE_NAME;
1006
1007 ARRAY_TO_STREAM(pp, name, len);
1008
1009 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1010 }
1011
1012 void btsnd_hcic_read_name(void) {
1013 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1014 uint8_t* pp = (uint8_t*)(p + 1);
1015
1016 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_CMD;
1017 p->offset = 0;
1018
1019 UINT16_TO_STREAM(pp, HCI_READ_LOCAL_NAME);
1020 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_CMD);
1021
1022 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1023 }
1024
1025 void btsnd_hcic_write_page_tout(uint16_t timeout) {
1026 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1027 uint8_t* pp = (uint8_t*)(p + 1);
1028
1029 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM2;
1030 p->offset = 0;
1031
1032 UINT16_TO_STREAM(pp, HCI_WRITE_PAGE_TOUT);
1033 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM2);
1034
1035 UINT16_TO_STREAM(pp, timeout);
1036
1037 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1038 }
1039
1040 void btsnd_hcic_write_scan_enable(uint8_t flag) {
1041 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1042 uint8_t* pp = (uint8_t*)(p + 1);
1043
1044 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1045 p->offset = 0;
1046
1047 UINT16_TO_STREAM(pp, HCI_WRITE_SCAN_ENABLE);
1048 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1049
1050 UINT8_TO_STREAM(pp, flag);
1051
1052 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1053 }
1054
1055 void btsnd_hcic_write_pagescan_cfg(uint16_t interval, uint16_t window) {
1056 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1057 uint8_t* pp = (uint8_t*)(p + 1);
1058
1059 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG;
1060 p->offset = 0;
1061
1062 UINT16_TO_STREAM(pp, HCI_WRITE_PAGESCAN_CFG);
1063 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG);
1064
1065 UINT16_TO_STREAM(pp, interval);
1066 UINT16_TO_STREAM(pp, window);
1067
1068 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1069 }
1070
1071 void btsnd_hcic_write_inqscan_cfg(uint16_t interval, uint16_t window) {
1072 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1073 uint8_t* pp = (uint8_t*)(p + 1);
1074
1075 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG;
1076 p->offset = 0;
1077
1078 UINT16_TO_STREAM(pp, HCI_WRITE_INQUIRYSCAN_CFG);
1079 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG);
1080
1081 UINT16_TO_STREAM(pp, interval);
1082 UINT16_TO_STREAM(pp, window);
1083
1084 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1085 }
1086
1087 void btsnd_hcic_write_auth_enable(uint8_t flag) {
1088 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1089 uint8_t* pp = (uint8_t*)(p + 1);
1090
1091 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1092 p->offset = 0;
1093
1094 UINT16_TO_STREAM(pp, HCI_WRITE_AUTHENTICATION_ENABLE);
1095 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1096
1097 UINT8_TO_STREAM(pp, flag);
1098
1099 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1100 }
1101
1102 void btsnd_hcic_write_dev_class(DEV_CLASS dev_class) {
1103 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1104 uint8_t* pp = (uint8_t*)(p + 1);
1105
1106 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM3;
1107 p->offset = 0;
1108
1109 UINT16_TO_STREAM(pp, HCI_WRITE_CLASS_OF_DEVICE);
1110 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM3);
1111
1112 DEVCLASS_TO_STREAM(pp, dev_class);
1113
1114 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1115 }
1116
1117 void btsnd_hcic_write_voice_settings(uint16_t flags) {
1118 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1119 uint8_t* pp = (uint8_t*)(p + 1);
1120
1121 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM2;
1122 p->offset = 0;
1123
1124 UINT16_TO_STREAM(pp, HCI_WRITE_VOICE_SETTINGS);
1125 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM2);
1126
1127 UINT16_TO_STREAM(pp, flags);
1128
1129 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1130 }
1131
1132 void btsnd_hcic_write_auto_flush_tout(uint16_t handle, uint16_t tout) {
1133 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1134 uint8_t* pp = (uint8_t*)(p + 1);
1135
1136 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_AUTOMATIC_FLUSH_TIMEOUT;
1137 p->offset = 0;
1138
1139 UINT16_TO_STREAM(pp, HCI_WRITE_AUTOMATIC_FLUSH_TIMEOUT);
1140 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_AUTOMATIC_FLUSH_TIMEOUT);
1141
1142 UINT16_TO_STREAM(pp, handle);
1143 UINT16_TO_STREAM(pp, tout);
1144
1145 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1146 }
1147
1148 void btsnd_hcic_read_tx_power(uint16_t handle, uint8_t type) {
1149 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1150 uint8_t* pp = (uint8_t*)(p + 1);
1151
1152 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_TX_POWER;
1153 p->offset = 0;
1154
1155 UINT16_TO_STREAM(pp, HCI_READ_TRANSMIT_POWER_LEVEL);
1156 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_TX_POWER);
1157
1158 UINT16_TO_STREAM(pp, handle);
1159 UINT8_TO_STREAM(pp, type);
1160
1161 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1162 }
1163
1164 void btsnd_hcic_write_link_super_tout(uint16_t handle, uint16_t timeout) {
1165 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1166 uint8_t* pp = (uint8_t*)(p + 1);
1167
1168 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT;
1169 p->offset = 0;
1170
1171 UINT16_TO_STREAM(pp, HCI_WRITE_LINK_SUPER_TOUT);
1172 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT);
1173
1174 UINT16_TO_STREAM(pp, handle);
1175 UINT16_TO_STREAM(pp, timeout);
1176
1177 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1178 }
1179
1180 void btsnd_hcic_write_cur_iac_lap(uint8_t num_cur_iac, LAP* const iac_lap) {
1181 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1182 uint8_t* pp = (uint8_t*)(p + 1);
1183
1184 p->len = HCIC_PREAMBLE_SIZE + 1 + (LAP_LEN * num_cur_iac);
1185 p->offset = 0;
1186
1187 UINT16_TO_STREAM(pp, HCI_WRITE_CURRENT_IAC_LAP);
1188 UINT8_TO_STREAM(pp, p->len - HCIC_PREAMBLE_SIZE);
1189
1190 UINT8_TO_STREAM(pp, num_cur_iac);
1191
1192 for (int i = 0; i < num_cur_iac; i++) LAP_TO_STREAM(pp, iac_lap[i]);
1193
1194 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1195 }
1196
1197 /******************************************
1198 * Lisbon Features
1199 ******************************************/
1200 void btsnd_hcic_sniff_sub_rate(uint16_t handle, uint16_t max_lat,
1201 uint16_t min_remote_lat,
1202 uint16_t min_local_lat) {
1203 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1204 uint8_t* pp = (uint8_t*)(p + 1);
1205
1206 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SNIFF_SUB_RATE;
1207 p->offset = 0;
1208
1209 UINT16_TO_STREAM(pp, HCI_SNIFF_SUB_RATE);
1210 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SNIFF_SUB_RATE);
1211
1212 UINT16_TO_STREAM(pp, handle);
1213 UINT16_TO_STREAM(pp, max_lat);
1214 UINT16_TO_STREAM(pp, min_remote_lat);
1215 UINT16_TO_STREAM(pp, min_local_lat);
1216
1217 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1218 }
1219
1220 /**** Extended Inquiry Response Commands ****/
1221 void btsnd_hcic_write_ext_inquiry_response(void* buffer, uint8_t fec_req) {
1222 BT_HDR* p = (BT_HDR*)buffer;
1223 uint8_t* pp = (uint8_t*)(p + 1);
1224
1225 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_EXT_INQ_RESP;
1226 p->offset = 0;
1227
1228 UINT16_TO_STREAM(pp, HCI_WRITE_EXT_INQ_RESPONSE);
1229 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_EXT_INQ_RESP);
1230
1231 UINT8_TO_STREAM(pp, fec_req);
1232
1233 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1234 }
1235
1236 void btsnd_hcic_io_cap_req_reply(const RawAddress& bd_addr, uint8_t capability,
1237 uint8_t oob_present, uint8_t auth_req) {
1238 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1239 uint8_t* pp = (uint8_t*)(p + 1);
1240
1241 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_IO_CAP_RESP;
1242 p->offset = 0;
1243
1244 UINT16_TO_STREAM(pp, HCI_IO_CAPABILITY_REQUEST_REPLY);
1245 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_IO_CAP_RESP);
1246
1247 BDADDR_TO_STREAM(pp, bd_addr);
1248 UINT8_TO_STREAM(pp, capability);
1249 UINT8_TO_STREAM(pp, oob_present);
1250 UINT8_TO_STREAM(pp, auth_req);
1251
1252 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1253 }
1254
1255 void btsnd_hcic_enhanced_set_up_synchronous_connection(
1256 uint16_t conn_handle, enh_esco_params_t* p_params) {
1257 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1258 uint8_t* pp = (uint8_t*)(p + 1);
1259
1260 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN;
1261 p->offset = 0;
1262
1263 UINT16_TO_STREAM(pp, HCI_ENH_SETUP_ESCO_CONNECTION);
1264 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN);
1265
1266 UINT16_TO_STREAM(pp, conn_handle);
1267 UINT32_TO_STREAM(pp, p_params->transmit_bandwidth);
1268 UINT32_TO_STREAM(pp, p_params->receive_bandwidth);
1269 UINT8_TO_STREAM(pp, p_params->transmit_coding_format.coding_format);
1270 UINT16_TO_STREAM(pp, p_params->transmit_coding_format.company_id);
1271 UINT16_TO_STREAM(pp,
1272 p_params->transmit_coding_format.vendor_specific_codec_id);
1273 UINT8_TO_STREAM(pp, p_params->receive_coding_format.coding_format);
1274 UINT16_TO_STREAM(pp, p_params->receive_coding_format.company_id);
1275 UINT16_TO_STREAM(pp,
1276 p_params->receive_coding_format.vendor_specific_codec_id);
1277 UINT16_TO_STREAM(pp, p_params->transmit_codec_frame_size);
1278 UINT16_TO_STREAM(pp, p_params->receive_codec_frame_size);
1279 UINT32_TO_STREAM(pp, p_params->input_bandwidth);
1280 UINT32_TO_STREAM(pp, p_params->output_bandwidth);
1281 UINT8_TO_STREAM(pp, p_params->input_coding_format.coding_format);
1282 UINT16_TO_STREAM(pp, p_params->input_coding_format.company_id);
1283 UINT16_TO_STREAM(pp, p_params->input_coding_format.vendor_specific_codec_id);
1284 UINT8_TO_STREAM(pp, p_params->output_coding_format.coding_format);
1285 UINT16_TO_STREAM(pp, p_params->output_coding_format.company_id);
1286 UINT16_TO_STREAM(pp, p_params->output_coding_format.vendor_specific_codec_id);
1287 UINT16_TO_STREAM(pp, p_params->input_coded_data_size);
1288 UINT16_TO_STREAM(pp, p_params->output_coded_data_size);
1289 UINT8_TO_STREAM(pp, p_params->input_pcm_data_format);
1290 UINT8_TO_STREAM(pp, p_params->output_pcm_data_format);
1291 UINT8_TO_STREAM(pp, p_params->input_pcm_payload_msb_position);
1292 UINT8_TO_STREAM(pp, p_params->output_pcm_payload_msb_position);
1293 UINT8_TO_STREAM(pp, p_params->input_data_path);
1294 UINT8_TO_STREAM(pp, p_params->output_data_path);
1295 UINT8_TO_STREAM(pp, p_params->input_transport_unit_size);
1296 UINT8_TO_STREAM(pp, p_params->output_transport_unit_size);
1297 UINT16_TO_STREAM(pp, p_params->max_latency_ms);
1298 UINT16_TO_STREAM(pp, p_params->packet_types);
1299 UINT8_TO_STREAM(pp, p_params->retransmission_effort);
1300
1301 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1302 }
1303
1304 void btsnd_hcic_enhanced_accept_synchronous_connection(
1305 const RawAddress& bd_addr, enh_esco_params_t* p_params) {
1306 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1307 uint8_t* pp = (uint8_t*)(p + 1);
1308
1309 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN;
1310 p->offset = 0;
1311
1312 UINT16_TO_STREAM(pp, HCI_ENH_ACCEPT_ESCO_CONNECTION);
1313 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN);
1314
1315 BDADDR_TO_STREAM(pp, bd_addr);
1316 UINT32_TO_STREAM(pp, p_params->transmit_bandwidth);
1317 UINT32_TO_STREAM(pp, p_params->receive_bandwidth);
1318 UINT8_TO_STREAM(pp, p_params->transmit_coding_format.coding_format);
1319 UINT16_TO_STREAM(pp, p_params->transmit_coding_format.company_id);
1320 UINT16_TO_STREAM(pp,
1321 p_params->transmit_coding_format.vendor_specific_codec_id);
1322 UINT8_TO_STREAM(pp, p_params->receive_coding_format.coding_format);
1323 UINT16_TO_STREAM(pp, p_params->receive_coding_format.company_id);
1324 UINT16_TO_STREAM(pp,
1325 p_params->receive_coding_format.vendor_specific_codec_id);
1326 UINT16_TO_STREAM(pp, p_params->transmit_codec_frame_size);
1327 UINT16_TO_STREAM(pp, p_params->receive_codec_frame_size);
1328 UINT32_TO_STREAM(pp, p_params->input_bandwidth);
1329 UINT32_TO_STREAM(pp, p_params->output_bandwidth);
1330 UINT8_TO_STREAM(pp, p_params->input_coding_format.coding_format);
1331 UINT16_TO_STREAM(pp, p_params->input_coding_format.company_id);
1332 UINT16_TO_STREAM(pp, p_params->input_coding_format.vendor_specific_codec_id);
1333 UINT8_TO_STREAM(pp, p_params->output_coding_format.coding_format);
1334 UINT16_TO_STREAM(pp, p_params->output_coding_format.company_id);
1335 UINT16_TO_STREAM(pp, p_params->output_coding_format.vendor_specific_codec_id);
1336 UINT16_TO_STREAM(pp, p_params->input_coded_data_size);
1337 UINT16_TO_STREAM(pp, p_params->output_coded_data_size);
1338 UINT8_TO_STREAM(pp, p_params->input_pcm_data_format);
1339 UINT8_TO_STREAM(pp, p_params->output_pcm_data_format);
1340 UINT8_TO_STREAM(pp, p_params->input_pcm_payload_msb_position);
1341 UINT8_TO_STREAM(pp, p_params->output_pcm_payload_msb_position);
1342 UINT8_TO_STREAM(pp, p_params->input_data_path);
1343 UINT8_TO_STREAM(pp, p_params->output_data_path);
1344 UINT8_TO_STREAM(pp, p_params->input_transport_unit_size);
1345 UINT8_TO_STREAM(pp, p_params->output_transport_unit_size);
1346 UINT16_TO_STREAM(pp, p_params->max_latency_ms);
1347 UINT16_TO_STREAM(pp, p_params->packet_types);
1348 UINT8_TO_STREAM(pp, p_params->retransmission_effort);
1349
1350 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1351 }
1352
1353 void btsnd_hcic_io_cap_req_neg_reply(const RawAddress& bd_addr,
1354 uint8_t err_code) {
1355 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1356 uint8_t* pp = (uint8_t*)(p + 1);
1357
1358 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY;
1359 p->offset = 0;
1360
1361 UINT16_TO_STREAM(pp, HCI_IO_CAP_REQ_NEG_REPLY);
1362 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY);
1363
1364 BDADDR_TO_STREAM(pp, bd_addr);
1365 UINT8_TO_STREAM(pp, err_code);
1366
1367 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1368 }
1369
1370 void btsnd_hcic_read_local_oob_data(void) {
1371 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1372 uint8_t* pp = (uint8_t*)(p + 1);
1373
1374 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_R_LOCAL_OOB;
1375 p->offset = 0;
1376
1377 UINT16_TO_STREAM(pp, HCI_READ_LOCAL_OOB_DATA);
1378 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_R_LOCAL_OOB);
1379
1380 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1381 }
1382
1383 void btsnd_hcic_read_local_oob_extended_data(void) {
1384 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1385 uint8_t* pp = (uint8_t*)(p + 1);
1386
1387 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_R_LOCAL_OOB_EXTENDED;
1388 p->offset = 0;
1389
1390 UINT16_TO_STREAM(pp, HCI_READ_LOCAL_OOB_EXTENDED_DATA);
1391 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_R_LOCAL_OOB_EXTENDED);
1392
1393 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1394 }
1395
1396 void btsnd_hcic_user_conf_reply(const RawAddress& bd_addr, bool is_yes) {
1397 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1398 uint8_t* pp = (uint8_t*)(p + 1);
1399
1400 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_UCONF_REPLY;
1401 p->offset = 0;
1402
1403 if (!is_yes) {
1404 /* Negative reply */
1405 UINT16_TO_STREAM(pp, HCI_USER_CONF_VALUE_NEG_REPLY);
1406 } else {
1407 /* Confirmation */
1408 UINT16_TO_STREAM(pp, HCI_USER_CONF_REQUEST_REPLY);
1409 }
1410
1411 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_UCONF_REPLY);
1412
1413 BDADDR_TO_STREAM(pp, bd_addr);
1414
1415 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1416 }
1417
1418 void btsnd_hcic_user_passkey_reply(const RawAddress& bd_addr, uint32_t value) {
1419 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1420 uint8_t* pp = (uint8_t*)(p + 1);
1421
1422 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_U_PKEY_REPLY;
1423 p->offset = 0;
1424
1425 UINT16_TO_STREAM(pp, HCI_USER_PASSKEY_REQ_REPLY);
1426 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_U_PKEY_REPLY);
1427
1428 BDADDR_TO_STREAM(pp, bd_addr);
1429 UINT32_TO_STREAM(pp, value);
1430
1431 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1432 }
1433
1434 void btsnd_hcic_user_passkey_neg_reply(const RawAddress& bd_addr) {
1435 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1436 uint8_t* pp = (uint8_t*)(p + 1);
1437
1438 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY;
1439 p->offset = 0;
1440
1441 UINT16_TO_STREAM(pp, HCI_USER_PASSKEY_REQ_NEG_REPLY);
1442 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY);
1443
1444 BDADDR_TO_STREAM(pp, bd_addr);
1445
1446 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1447 }
1448
1449 void btsnd_hcic_rem_oob_reply(const RawAddress& bd_addr, const Octet16& c,
1450 const Octet16& r) {
1451 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1452 uint8_t* pp = (uint8_t*)(p + 1);
1453
1454 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REM_OOB_REPLY;
1455 p->offset = 0;
1456
1457 UINT16_TO_STREAM(pp, HCI_REM_OOB_DATA_REQ_REPLY);
1458 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REM_OOB_REPLY);
1459
1460 BDADDR_TO_STREAM(pp, bd_addr);
1461 ARRAY16_TO_STREAM(pp, c.data());
1462 ARRAY16_TO_STREAM(pp, r.data());
1463
1464 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1465 }
1466
1467 void btsnd_hcic_rem_oob_neg_reply(const RawAddress& bd_addr) {
1468 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1469 uint8_t* pp = (uint8_t*)(p + 1);
1470
1471 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY;
1472 p->offset = 0;
1473
1474 UINT16_TO_STREAM(pp, HCI_REM_OOB_DATA_REQ_NEG_REPLY);
1475 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY);
1476
1477 BDADDR_TO_STREAM(pp, bd_addr);
1478
1479 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1480 }
1481
1482 /**** end of Simple Pairing Commands ****/
1483
1484 /*************************
1485 * End of Lisbon Commands
1486 *************************/
1487
1488 void btsnd_hcic_read_rssi(uint16_t handle) {
1489 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1490 uint8_t* pp = (uint8_t*)(p + 1);
1491
1492 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
1493 p->offset = 0;
1494
1495 UINT16_TO_STREAM(pp, HCI_READ_RSSI);
1496 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
1497
1498 UINT16_TO_STREAM(pp, handle);
1499
1500 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1501 }
1502
1503 static void read_encryption_key_size_complete(
1504 ReadEncKeySizeCb cb, uint8_t* return_parameters,
1505 uint16_t /* return_parameters_length */) {
1506 uint8_t status;
1507 uint16_t handle;
1508 uint8_t key_size;
1509 STREAM_TO_UINT8(status, return_parameters);
1510 STREAM_TO_UINT16(handle, return_parameters);
1511 STREAM_TO_UINT8(key_size, return_parameters);
1512
1513 std::move(cb).Run(status, handle, key_size);
1514 }
1515
1516 void btsnd_hcic_read_encryption_key_size(uint16_t handle, ReadEncKeySizeCb cb) {
1517 constexpr uint8_t len = 2;
1518 uint8_t param[len];
1519 memset(param, 0, len);
1520
1521 uint8_t* p = param;
1522 UINT16_TO_STREAM(p, handle);
1523
1524 btu_hcif_send_cmd_with_cb(FROM_HERE, HCI_READ_ENCR_KEY_SIZE, param, len,
1525 base::Bind(&read_encryption_key_size_complete, base::Passed(&cb)));
1526 }
1527
1528 void btsnd_hcic_read_failed_contact_counter(uint16_t handle) {
1529 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1530 uint8_t* pp = (uint8_t*)(p + 1);
1531
1532 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE;
1533 p->offset = 0;
1534
1535 UINT16_TO_STREAM(pp, HCI_READ_FAILED_CONTACT_COUNTER);
1536 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE);
1537
1538 UINT16_TO_STREAM(pp, handle);
1539
1540 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1541 }
1542
1543 void btsnd_hcic_enable_test_mode(void) {
1544 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1545 uint8_t* pp = (uint8_t*)(p + 1);
1546
1547 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_CMD;
1548 p->offset = 0;
1549
1550 UINT16_TO_STREAM(pp, HCI_ENABLE_DEV_UNDER_TEST_MODE);
1551 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_CMD);
1552
1553 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1554 }
1555
1556 void btsnd_hcic_write_inqscan_type(uint8_t type) {
1557 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1558 uint8_t* pp = (uint8_t*)(p + 1);
1559
1560 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1561 p->offset = 0;
1562
1563 UINT16_TO_STREAM(pp, HCI_WRITE_INQSCAN_TYPE);
1564 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1565
1566 UINT8_TO_STREAM(pp, type);
1567
1568 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1569 }
1570
1571 void btsnd_hcic_write_inquiry_mode(uint8_t mode) {
1572 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1573 uint8_t* pp = (uint8_t*)(p + 1);
1574
1575 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1576 p->offset = 0;
1577
1578 UINT16_TO_STREAM(pp, HCI_WRITE_INQUIRY_MODE);
1579 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1580
1581 UINT8_TO_STREAM(pp, mode);
1582
1583 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1584 }
1585
1586 void btsnd_hcic_write_pagescan_type(uint8_t type) {
1587 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1588 uint8_t* pp = (uint8_t*)(p + 1);
1589
1590 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1;
1591 p->offset = 0;
1592
1593 UINT16_TO_STREAM(pp, HCI_WRITE_PAGESCAN_TYPE);
1594 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1);
1595
1596 UINT8_TO_STREAM(pp, type);
1597
1598 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1599 }
1600
1601 static void btsnd_hcic_vendor_spec_complete(tBTM_VSC_CMPL_CB* p_vsc_cplt_cback,
1602 uint16_t opcode, uint8_t* data,
1603 uint16_t len) {
1604 /* If there was a callback address for vcs complete, call it */
1605 if (p_vsc_cplt_cback) {
1606 tBTM_VSC_CMPL vcs_cplt_params;
1607 vcs_cplt_params.opcode = opcode;
1608 vcs_cplt_params.param_len = len;
1609 vcs_cplt_params.p_param_buf = data;
1610 /* Call the VSC complete callback function */
1611 (*p_vsc_cplt_cback)(&vcs_cplt_params);
1612 }
1613 }
1614
1615 void btsnd_hcic_vendor_spec_cmd(uint16_t opcode, uint8_t len, uint8_t* p_data,
1616 tBTM_VSC_CMPL_CB* p_cmd_cplt_cback) {
1617 uint16_t v_opcode = HCI_GRP_VENDOR_SPECIFIC | opcode;
1618
1619 btu_hcif_send_cmd_with_cb(
1620 FROM_HERE, v_opcode, p_data, len,
1621 base::BindOnce(&btsnd_hcic_vendor_spec_complete,
1622 base::Unretained(p_cmd_cplt_cback), v_opcode));
1623 }
1624
1625 void btsnd_hcic_configure_data_path(hci_data_direction_t data_path_direction,
1626 uint8_t data_path_id,
1627 std::vector<uint8_t> vendor_config) {
1628 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1629 uint8_t* pp = (uint8_t*)(p + 1);
1630 uint8_t size = static_cast<uint8_t>(vendor_config.size());
1631 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CONFIGURE_DATA_PATH + size;
1632 p->offset = 0;
1633
1634 UINT16_TO_STREAM(pp, HCI_CONFIGURE_DATA_PATH);
1635 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CONFIGURE_DATA_PATH + size);
1636 UINT8_TO_STREAM(pp, data_path_direction);
1637 UINT8_TO_STREAM(pp, data_path_id);
1638 UINT8_TO_STREAM(pp, vendor_config.size());
1639 if (size != 0) {
1640 ARRAY_TO_STREAM(pp, vendor_config.data(), size);
1641 }
1642
1643 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1644 }
1645
1646 namespace bluetooth::legacy::hci {
1647 class InterfaceImpl : public Interface {
1648 void Disconnect(uint16_t handle, uint8_t reason) const override {
1649 btsnd_hcic_disconnect(handle, reason);
1650 }
1651 void ChangeConnectionPacketType(uint16_t handle,
1652 uint16_t packet_types) const override {
1653 btsnd_hcic_change_conn_type(handle, packet_types);
1654 }
1655 void StartRoleSwitch(const RawAddress& bd_addr, uint8_t role) const override {
1656 btsnd_hcic_switch_role(bd_addr, role);
1657 }
1658 void ConfigureDataPath(hci_data_direction_t data_path_direction,
1659 uint8_t data_path_id,
1660 std::vector<uint8_t> vendor_config) const override {
1661 btsnd_hcic_configure_data_path(data_path_direction, data_path_id,
1662 vendor_config);
1663 }
1664 void SendVendorSpecificCmd(unsigned short opcode,
1665 unsigned char len, unsigned char* param, void (*cb)(tBTM_VSC_CMPL*)) const override {
1666 btsnd_hcic_vendor_spec_cmd(opcode, len, param, cb);
1667 }
1668 };
1669
1670 namespace {
1671 const InterfaceImpl interface_;
1672 }
1673
1674 const Interface& GetInterface() { return interface_; }
1675 } // namespace bluetooth::legacy::hci
1676
1677 void btsnd_hcic_flow_spec(uint16_t handle, uint8_t unused, uint8_t direction,
1678 uint8_t service_type, uint32_t token_rate,
1679 uint32_t token_size, uint32_t peak, uint32_t latency){
1680
1681 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE);
1682 uint8_t* pp = (uint8_t*)(p + 1);
1683
1684 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_FLOW_SPECIFICATION;
1685 p->offset = 0;
1686
1687 UINT16_TO_STREAM(pp, HCI_FLOW_SPECIFICATION);
1688 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_FLOW_SPECIFICATION);
1689
1690 UINT16_TO_STREAM(pp, handle);
1691 UINT8_TO_STREAM(pp, unused);
1692 UINT8_TO_STREAM(pp, direction);
1693 UINT8_TO_STREAM(pp, service_type);
1694 UINT32_TO_STREAM(pp, token_rate);
1695 UINT32_TO_STREAM(pp, token_size);
1696 UINT32_TO_STREAM(pp, peak);
1697 UINT32_TO_STREAM(pp, latency);
1698
1699 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
1700 }
本文探讨了一种计算特定字符串(goodstring)在一个由随机单词组成的长字符串(longstring)中出现次数的期望值的方法。关键发现指出，在longstring中某个位置出现goodstring的次数仅与前几个相关单词有关，并且这些单词的选择是相互独立的。这一结论有助于解决当longstring长度远大于goodstring长度时的计算问题。
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