homework 2025.01.04

Info: ******************************************************************* Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Info: Processing started: Mon May 19 19:01:30 2025 Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Info: Processing started: Mon May 19 19:01:30 2025 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off homework -c homework Warning (20028): Parallel compilation is not licensed and has been disabled Warning (10463): Verilog HDL Declaration warning at homework.v(13): "enum" is SystemVerilog-2005 keyword Error (10170): Verilog HDL syntax error at homework.v(13) near text "logic"; expecting ";" Error (10170): Verilog HDL syntax error at homework.v(18) near text "}"; expecting ";" Error (10112): Ignored design unit "traffic_light_controller" at homework.v(1) due to previous errors Info (12021): Found 0 design units, including 0 entities, in source file homework.v Info (144001): Generated suppressed messages file D:/Quartus2/output_files/homework.map.smsg Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 3 errors, 2 warnings Error: Peak virtual memory: 4583 megabytes Error: Processing ended: Mon May 19 19:01:31 2025 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:01 Error: Peak virtual memory: 4583 megabytes Error: Processing ended: Mon May 19 19:01:31 2025 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:01 Error (293001): Quartus II Full Compilation was unsuccessful. 5 errors, 2 warnings 结果报错了,请你改正重新发我代码
05-20
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