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原创 C语言常见易忽视规则
1. 每个函数定义结束之后以及每个文件结束之后都要加一个或若干个空行。2. 在一个函数体内，变量定义与函数语句之间要加空行。3. 逻揖上密切相关的语句之间不加空行，其它地方应加空行分隔。4. 用缩行显示程序结构，使排版整齐，缩进量统一使用4个字符（不用TAB ）。5. 在函数体的开始、结构/联合的定义、枚举的定义以及循环、判断等语...
2020-04-07 08:03:56
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原创 嵌入式 C 语言开发常见错误第一篇
常易忽视C开发时错误点，面试也容易出现的题目break1.一般我们用switch(){case () :执行该case条件的语句；break;default:;break;}注意：break关键字，只能用于跳出最近那层循环语句(for ,while,do…while)或者switch语句，而不是if语句；看起来像很简单，但是到嵌套许多循环时，极其容易忽略。sizeof(这是关键字，不是函数)sizeof作用是返回一个对象或者类型所占的内存字节数，对绝大多数编译器而言，返回值为无符号整形数
2021-03-14 11:41:00
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AD9833.rar
This low power DDS device is a numerically controlled oscillator employing a phase accumulator, a SIN ROM and a 10-bit D/A converter integrated on a single CMOS chip. Clock rates up to 25 MHz are supported
with a power supply from +2.3 V to +5.5 V. Capability for phase modulation and frequency modulation is provided. Frequency accuracy can be controlled to one part in 0.25 billion. Modulation is effected by loading registers through the serial interface. The AD9833 offers a variety of output waveforms from the VOUT pin. The SIN ROM can be bypassed so that a linear up/down ramp is output from the DAC. If the SIN ROM is not by-passed, a sinusoidal output is available. Also, if a clock output is required, the MSB of the DAC data can be output. The digital section is internally operated at +2.5 V, irrespective of the value of VDD, by an on board regulator which steps down VDD to +2.5 V, when VDD exceeds +2.5 V. The AD9833 has a power-down function (SLEEP). This allows sections of the device which are not being used to be powered down, thus minimising the current consumption of the part e.g the DAC can be powered down when a clock output is being generated. The
2020-04-07
AD9833.rar
基于DDS芯片AD9833的低频信号发生器，基于Mega8单片机和AD9833的正弦波信号发生器，基于单片机和AD9833的信号发生器的设计，DDS AD9850，仅供参考
2020-04-07
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