Linux kernel study note -- Translation Lookaside Buffers

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本文探讨了Translation Look-aside Buffers (TLB)的工作原理，一种用于加速线性地址转换的缓存机制。在多处理器系统中，每个CPU拥有独立的本地TLB，无需同步，因为不同CPU上的进程可能将相同的线性地址映射到不同的物理地址。修改CR3寄存器时，硬件会自动使所有本地TLB条目失效。

Translation Look-aside Buffers ( TLB )

12/7/2019, 8:29:19 AM
Besides general-purpose hardware caches, 80 x 86 processors include another cache called Translation Lookaside Buffers (TLB) to speed up linear address translation. When a linear address is used for the first time, the corresponding physical address is computed through slow accesses to the Page Tables in RAM. The physical address is then stored in a TLB entry so that further references to the same linear address can be quickly translated.
In a multiprocessor system, each CPU has its own TLB, called the local TLB of the CPU. Contrary to the hardware cache, the responding entries of the TLB need not be synchronized, because processes running on the existing CPUs may associate the same linear address with different physical ones.
When the cr3 control register of a CPU is modified, the hardware automatically invalidates all entries of the local TLB, because a new set of page tables is in use and the TLBs are pointing to old data.