module JSQ1KHZ(clk1khz,clk1hz,clk05hz,reset,clk);
input clk,reset;
output clk1khz,clk1hz,clk05hz;
reg[3:0]qa,qb,qc,qd,qe,qf,qg,gh;
reg clk1khz,clk1hz,clk05hz;
always@(posedge clk or negedge reset)
begin
if(!reset) begin {qa,qb,qc,qd,qe,qf,qg,gh}<=27'd00000000;clk1hz<=0;clk05hz<=0; end
else begin
if({qa,qb,qc,qd,qe,qf,qg,gh}==27'd99999999) begin {qa,qb,qc,qd,qe,qf,qg,gh}<=27'd00000000;clk1hz<=0;clk05hz<=0; end
else begin
if({qa,qb,qc,qd,qe,qf,qg,gh}==27'd75000000) begin clk1hz<=1;clk05hz<=1;{qa,qb,qc,qd,qe,qf,qg,gh}<={qa,qb,qc,qd,qe,qf,qg,gh}+4'h1; end
else begin
if({qa,qb,qc,qd,qe,qf,qg,gh}==27'd50000000)begin clk1hz<=0;clk05hz<=1;{qa,qb,qc,qd,qe,qf,qg,gh}<={qa,qb,qc,qd,qe,qf,qg,gh}+4'h1; end
else begin if({qa,qb,qc,qd,qe,qf,qg,gh}==27'd25000000)begin clk1hz<=1;clk05hz<=0;{qa,qb,qc,qd,qe,qf,qg,gh}<={qa,qb,qc,qd,qe,qf,qg,gh}+1; end
else begin {qa,qb,qc,qd,qe,qf,qg,gh}<={qa,qb,qc,qd,qe,qf,qg,gh}+4'h1; clk1khz<=qe[2]; end
end
end
end
end
end
endmodule