Bits Bytes and Words

最新推荐文章于 2024-12-31 20:01:47 发布
最新推荐文章于 2024-12-31 20:01:47 发布
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分类专栏： Storage Linux

Bits, Bytes and Words

A bit is a BInary digiT. So a bit is a zero or a one. Bits can be implemented in computer hardware using switches. If the switch is on then the bit is one and if the switch is off then the bit is zero. A bit is limited to representing two values. 

Since the alphabet contains more than two letters, a letter cannot be represented by a bit. A byte is a sequence of bits. Since the mid 1960's a byte has been 8 bits in length. 01000001 is an example of a byte. Since there are 8 bits in a byte there are 28 different possible sequences for one byte, ranging from 00000000 to 11111111. This means that a byte can be used to represent any type of value with no more than 28 = 256 possible values. Since the number of things that you can enter on a computer keyboard is smaller than 256 (including all keystoke pairs, like shift or control plus another key), a code for a keystoke is represented with a code within a byte.

Since characters (letters, decimal digits and special characters such as punctuation marks, etc) can be represented with bytes, a standard is needed to insure that the code that's used on your computer is the same as the code that is used on mine. There are two standard codes that use one byte to represent a character, ASCII (ass'-key) and EBCDIC (ib'-suh-dik). ASCII, the American Standard Code for Information Interchange, is the code that is most commonly used today. EBCDIC, Extended Binary Coded Decimal Interchange Code, was used by IBM on its large mainframe computers in the past. Wikipedia has more than you want to know about ASCII and EBCDIC. Since these codes are limited to 256 possible combinations, certain character sets, such as Chinese, Arabic, Japanese, Klingon and others, cannot be represented using these codes. This problem is solved by using another code, Unicode, which uses 2 bytes for each character. This extension allows 216 different symbols to be represented, a total of 65,536. The use of Unicode gives more flexibility in the representation of data. The drawback of using Unicode is that it takes twice as much space to store the same number of characters.

A word is the number of bits that are manipulated as a unit by the particular CPU of the computer. Today most CPUs have a word size of 32 or 64 bits. For example, the notebook computer that I bought in May 2008 contains a core 2 duo 64 bit processor. Data is fetched from memory to the processor in word size chunks and manipulated by the ALU in word size chunks. All other things being equal, (and they never are), larger word size implies faster and more flexible processing.

Further Information

Wikipedia contains exhaustive information about bits, bytes and words.

howSTUFFworks also has an article on (How Bits and Bytes Work)


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19.5 MCAN 19.5.1 Overview The M_CAN performs communication according to ISO11898-1:2015. Additional transceiver hardware is required for connection to the physical layer. The message storage is intended to be a single-ported Message RAM outside of the module. It is connected to the M_CAN via the Generic Master Interface. All functions concerning the handling of messages are implemented by the Rx Handler and the Tx Handler. The Rx Handler manages message acceptance filtering, the transfer of received messages from the CAN Core to the Message RAM as well as providing receive message status information. The Tx Handler is responsible for the transfer of transmit messages from the Message RAM to the CAN Core as well as providing transmit status information. Acceptance filtering is implemented by a combination of up to 128 filter elements where each one can be configured as a range, as a bit mask, or as a dedicated ID filter. 19.5.1.1 Features • Conform with ISO 11898-1:2015 • CAN FD with up to 64 data bytes supported • CAN Error Logging • AUTOSAR optimized • SAE J1939 optimized • Improved acceptance filtering • Two configurable Receive FIFOs • Separate signalling on reception of High Priority Messages • Up to 64 dedicated Receive Buffers • Up to 32 dedicated Transmit Buffers • Configurable Transmit FIFO • Configurable Transmit Queue • Configurable Transmit Event FIFO • Direct Message RAM access for Host CPU • Programmable loop-back test mode • Maskable module interrupts • Two clock domains (CAN clock and Host clock) • Power-down support R01UH0517EJ0130 Rev.1.30 Page 996 of 3095 Dec 25, 2017 RH850/P1x-C Section 19 CAN Controller (MCAN) ISO CANFD ISO 11898-1:2015 19.5.1.2 Block Diagram CAN Core: CAN Protocol Controller and Rx/Tx Shift Register. Handles all ISO 11898-1 protocol functions. Supports 11-bit and 29-bit identifiers. Sync: Synchronizes signals from the Host clock domain to the CAN clock domain and vice versa. Clk: Synchronizes reset signal to the Host clock domain and to the CAN clock domain. Cfg & Ctrl: CAN Core related configuration and control bits. Interrupt & Timestamp: Interrupt control and 16-bit CAN bit time counter for receive and transmit timestamp generation. An externally generated 16-bit vector may substitute the integrated 16-bit CAN bit time counter for receive and transmit timestamp generation. Figure 19.3 M_TTCAN Block Diagram m_can_rx m_can_tx Sync Rx Handler Cfg & Ctrl Acceptance Filter Interrupt & Generic Master IF Timestamp Tx_State Tx_Req Cfg & Ctrl M_CAN CAN Core Tx Handler Cfg & Ctrl Tx Prioritization Rx_State CAN Clock Domain Host Clock Domain Generic Slave IF Clk Host IF Memory IF 8/16/32 32 Extension IF R01UH0517EJ0130 Rev.1.30 Page 997 of 3095 Dec 25, 2017 RH850/P1x-C Section 19 CAN Controller (MCAN) ISO CANFD ISO 11898-1:2015 Tx Handler: Controls the message transfer from the external Message RAM to the CAN Core. A maximum of 32 Tx Buffers can be configured for transmission. Tx buffers can be used as dedicated Tx Buffers, as Tx FIFO, part of a Tx Queue, or as a combination of them. A Tx Event FIFO stores Tx timestamps together with the corresponding Message ID. Transmit cancellation is also supported. Rx Handler: Controls the transfer of received messages from the CAN Core to the external Message RAM. The Rx Handler supports two Receive FIFOs, each of configurable size, and up to 64 dedicated Rx Buffers for storage of all messages that have passed acceptance filtering. A dedicated Rx Buffer, in contrast to a Receive FIFO, is used to store only messages with a specific identifier. An Rx timestamp is stored together with each message. Up to 128 filters can be defined for 11-bit IDs and up to 64 filters for 29- bit IDs. Generic Slave Interface: Connects the M_CAN to a customer specific Host CPU. The Generic Slave Interface is capable to connect to an 8/16/32-bit bus to support a wide range of interconnection structures. Generic Master Interface: Connects the M_CAN to a local 32-bit Message RAM. The implemented Message RAM size is 2K • 32 bit. Extension Interface: All flags from the Interrupt Register MCANnIR as well as selected internal status and control signals are routed to this interface. The interface is intended for connection of the M_CAN to a module￾external interrupt unit or to other module-external components. The connection of these signals is optional. 19.5.1.3 Dual Clock Sources To improve the EMC behavior, a spread spectrum clock can be used for the Host clock domain m_can_hclk (CLK_HSB). Due to the high precision clocking requirements of the CAN Core, a separate clock without any modulation has to be provided as m_can_cclk (CLKP_H2). Within the M_TTCAN module there is a synchronization mechanism implemented to ensure save data transfer between the two clock domains. NOTE In order to achieve a stable function of the M_TTCAN, the Host clock must always be faster than or equal to the CAN clock. Also the modulation depth of the spread spectrum clock has to be regarded. 19.5.1.4 Dual Interrupt Lines The module provides two interrupt lines. Interrupts can be routed either to m_can_int0 (INTMCANnI0) or to m_can_int1 (INTMCANnI1). By default all interrupts are routed to interrupt line m_can_int0 (INTMCANnI0). By programming MCANnILE.EINT0 and MCANnILE.EINT1 the interrupt lines can be enabled or disabled separately. 19.5.2.4 Message RAM For storage of Rx/Tx messages and for storage of the filter configuration a single- or dual-ported Message RAM has to be connected to the M_CAN module. (1) Message RAM Configuration The Message RAM has a width of 32 bits. In case parity checking or ECC is used a respective number of bits has to be added to each word. The M_CAN module can be configured to allocate up to 4352 words in the Message RAM. It is not necessary to configure each of the sections listed in Figure 19.4, Message RAM Configuration, nor is there any restriction with respect to the sequence of the sections. When operated in CAN FD mode the required Message RAM size strongly depends on the element size configured for Rx FIFO0, Rx FIFO1, Rx Buffers, and Tx Buffers via MCANnRXESC.F0DS, MCANnRXESC.F1DS, MCANnRXESC.RBDS, and MCANnTXESC.TBDS. When the M_CAN addresses the Message RAM it addresses 32-bit words, not single bytes. The configurable start addresses are 32-bit word addresses i.e. only bits 15 to 2 are evaluated, the two least significant bits are ignored. NOTE The M_CAN does not check for erroneous configuration of the Message RAM. Especially the configuration of the start addresses of the different sections and the number of elements of each section has to be done carefully to avoid falsification or loss of data. Figure 19.4 Message RAM Configuration Rx FIFO 0 Rx FIFO 1 Tx Buffers Tx Event FIFO 11-bit Filter 29-bit Filter max. 2K words 0-64 elements / 0-1152 words 0-64 elements / 0-1152 words 0-32 elements / 0-576 words 0-32 elements / 0-64 words 0-128 elements / 0-128 words 0-64 elements / 0-128 words 32 bit MCANnRXF0C.F0SA MCANnRXF1C.F1SA MCANnTXBC.TBSA MCANnTXEFC.EFSA MCANnSIDFC.FLSSA MCANnXIDFC.FLESA Start Address Rx Buffers 0-64 elements / 0-1152 words MCANnRXBC.RBSA R01UH0517EJ0130 Rev.1.30 Page 1053 of 3095 Dec 25, 2017 RH850/P1x-C Section 19 CAN Controller (MCAN) ISO CANFD ISO 11898-1:2015 (2) Rx Buffer and FIFO Element Up to 64 Rx Buffers and two Rx FIFOs can be configured in the Message RAM. Each Rx FIFO section can be configured to store up to 64 received messages. The structure of a Rx Buffer / FIFO element is shown in Table 19.60 below. The element size can be configured for storage of CAN FD messages with up to 64 bytes data field via register MCANnRXESC. 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