ISE 里的timing report

ISE综合后能够得到这样一个timing report

   Minimum period: 1.124ns (Maximum Frequency: 889.318MHz)
   Minimum input arrival time before clock: 3.138ns
   Maximum output required time after clock: 51.163ns
   Maximum combinational path delay: No path found

 

各个时间的解释如下：

 

The maximum path from all primary inputs to the sequential elements: Minimum input arrival time before clock -- Path1 in the attached screenshot

 

The path from any clock to any clock in the design: Minimum period -- Path2

 

The maximum path from the sequential elements to all primary outputs: Maximum output required time before clock -- Path3

 

The maximum path from inputs to outputs: Maximum combinational path delay -- Path4

 

如下图：

网上有些朋友说：

 Minimum input arrival time before clock 是setup time
Maximum output required time after clock 是hold time

http://oursogo.com/viewthread.php?tid=707796&extra=page%3D2

但是我觉得奇怪，如果是setup time的话，应该是最大频率计算的一个部分，但是其实这个timing report是没有算的

所以，这样的说法是有误解的。

 有时会出现

   Minimum period: No path found
   Minimum input arrival time before clock: 3.536ns
   Maximum output required time after clock: 3.293ns
   Maximum combinational path delay: No path found

 

Minimum period: No path found

那是因为组合逻辑的前后没有寄存器

   Maximum combinational path delay: No path found

那是因为没有PATH4