start_kernel()--->trap_init();
start_kernel()---->init_IRQ();
arch/arm/kernel/traps.c:
//New kernel version is
early_trap_init(void), and early_trap_init(void) called by
setup_arch(void) in arch/arm/kernel/setup.c
void __init trap_init(void)
{
unsigned long vectors = CONFIG_VECTORS_BASE;/* Where the list will be saved */
/* entry-armv.S */
extern char __stubs_start[], __stubs_end[];
extern char __vectors_start[], __vectors_end[];
extern char __kuser_helper_start[], __kuser_helper_end[];
int kuser_sz = __kuser_helper_end - __kuser_helper_start;
/*
* Copy the vectors, stubs and kuser helpers (in entry-armv.S)
* into the vector page, mapped at 0xffff0000, and ensure these
* are visible to the instruction stream.
*/
memcpy((void *)vectors, __vectors_start, __vectors_end - __vectors_start);
memcpy((void *)vectors + 0x200, __stubs_start, __stubs_end - __stubs_start);
memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz);
/*
* Copy signal return handlers into the vector page, and
* set sigreturn to be a pointer to these.
*/
memcpy((void *)KERN_SIGRETURN_CODE, sigreturn_codes, sizeof(sigreturn_codes));
flush_icache_range(vectors, vectors + PAGE_SIZE);
modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
}
The CONFIG_VECTORS_BASE usually defined in autoconf.c, and the value is 0xffff0000,
The following is about __vectors_start,__vectors_end, __stubs_start, __stubs_end
arch/arm/kernel/entry-armv.S:
.globl __vectors_start
__vectors_start:
swi SYS_ERROR0
b vector_und + stubs_offset
ldr pc, .LCvswi + stubs_offset
b vector_pabt + stubs_offset
b vector_dabt + stubs_offset
b vector_addrexcptn + stubs_offset
b vector_irq + stubs_offset
b vector_fiq + stubs_offset
.globl __vectors_end
__vectors_end:
.data
vector_irq & vector_fiq are defined between __stubs_start and __stubs_end .
So, after traps_init(), there must be a jump list at 0xffff0000, if there's a IRQ, vector_irq+stubs_offet is the right way.
-------------------------------------------------------------------------------------------------------------------------- ------- -------
Afer traps_init(), start_kernel() will call init_IRQ(), init_IRQ() initialize GIDT.
arm/arm/kernel/Irq.c:
void __init init_IRQ(void)
{
int irq;
/* Initialize GIDT*/
for (irq = 0; irq < NR_IRQS; irq++)
irq_desc[irq].status |= IRQ_NOREQUEST | IRQ_DELAYED_DISABLE |
IRQ_NOPROBE;
#ifdef CONFIG_SMP
bad_irq_desc.affinity = CPU_MASK_ALL;
bad_irq_desc.cpu = smp_processor_id();
#endif
init_arch_irq(); /* paltform relate interrupt initialization*/
}
-------------------------------------------------------------------------------------------------------------------------- ------- -------
It have NR_IRQS of interrupt types in kernel , every interrupt type has its descriptor
As to smdk_2410, init_arch_irq() same as s3c24xx_init_irq(),
setup_arch() just band the s3c24xx_init_irq() to init_arch_irq()
arch/arm/mach-s3c2410/Irq.c:
/* s3c24xx_init_irq
*
* Initialise S3C2410 IRQ system
*/
void __init s3c24xx_init_irq(void)
{
unsigned long pend;
unsigned long last;
int irqno;
int i;
irqdbf("s3c2410_init_irq: clearing interrupt status flags/n");
/* first, clear all interrupts pending... */
last = 0;
for (i = 0; i < 4; i++) {
pend = __raw_readl(S3C24XX_EINTPEND);
if (pend == 0 || pend == last)
break;
__raw_writel(pend, S3C24XX_EINTPEND);
printk("irq: clearing pending ext status %08x/n", (int)pend);
last = pend;
}
last = 0;
for (i = 0; i < 4; i++) {
pend = __raw_readl(S3C2410_INTPND);
if (pend == 0 || pend == last)
break;
__raw_writel(pend, S3C2410_SRCPND);
__raw_writel(pend, S3C2410_INTPND);
printk("irq: clearing pending status %08x/n", (int)pend);
last = pend;
}
last = 0;
for (i = 0; i < 4; i++) {
pend = __raw_readl(S3C2410_SUBSRCPND);
if (pend == 0 || pend == last)
break;
printk("irq: clearing subpending status %08x/n", (int)pend);
__raw_writel(pend, S3C2410_SUBSRCPND);
last = pend;
}
/* register the main interrupts */
irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers/n");
for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
/* set all the s3c2410 internal irqs */
switch (irqno) {
/* deal with the special IRQs (cascaded) */
case IRQ_EINT4t7:
case IRQ_EINT8t23:
case IRQ_UART0:
case IRQ_UART1:
case IRQ_UART2:
case IRQ_ADCPARENT:
set_irq_chip(irqno, &s3c_irq_level_chip);
set_irq_handler(irqno, do_level_IRQ);
break;
case IRQ_RESERVED6:
case IRQ_RESERVED24:
/* no IRQ here */
break;
default: /*IRQ_WDT just like this */
//irqdbf("registering irq %d (s3c irq)/n", irqno);
set_irq_chip(irqno, &s3c_irq_chip); /* set chip*/
set_irq_handler(irqno, do_edge_IRQ); /* set handler/
set_irq_flags(irqno, IRQF_VALID); /* set flags*/
}
}
/* setup the cascade irq handlers */
set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint);
set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint);
set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
/* external interrupts */
for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
irqdbf("registering irq %d (ext int)/n", irqno);
set_irq_chip(irqno, &s3c_irq_eint0t4);
set_irq_handler(irqno, do_edge_IRQ);
set_irq_flags(irqno, IRQF_VALID);
}
for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
irqdbf("registering irq %d (extended s3c irq)/n", irqno);
set_irq_chip(irqno, &s3c_irqext_chip);
set_irq_handler(irqno, do_edge_IRQ);
set_irq_flags(irqno, IRQF_VALID);
}
/* register the uart interrupts */
irqdbf("s3c2410: registering external interrupts/n");
for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
irqdbf("registering irq %d (s3c uart0 irq)/n", irqno);
set_irq_chip(irqno, &s3c_irq_uart0);
set_irq_handler(irqno, do_level_IRQ);
set_irq_flags(irqno, IRQF_VALID);
}
for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
irqdbf("registering irq %d (s3c uart1 irq)/n", irqno);
set_irq_chip(irqno, &s3c_irq_uart1);
set_irq_handler(irqno, do_level_IRQ);
set_irq_flags(irqno, IRQF_VALID);
}
for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
irqdbf("registering irq %d (s3c uart2 irq)/n", irqno);
set_irq_chip(irqno, &s3c_irq_uart2);
set_irq_handler(irqno, do_level_IRQ);
set_irq_flags(irqno, IRQF_VALID);
}
for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
irqdbf("registering irq %d (s3c adc irq)/n", irqno);
set_irq_chip(irqno, &s3c_irq_adc);
set_irq_handler(irqno, do_edge_IRQ);
set_irq_flags(irqno, IRQF_VALID);
}
irqdbf("s3c2410: registered interrupt handlers/n");
}
set_irq_chip
kernel/irq/chip.c:
/**
* set_irq_chip - set the irq chip for an irq
* @irq: irq number
* @chip: pointer to irq chip description structure
*/
int set_irq_chip(unsigned int irq, struct irq_chip *chip)
{
struct irq_desc *desc;
unsigned long flags;
if (irq >= NR_IRQS) {
printk(KERN_ERR "Trying to install chip for IRQ%d/n", irq);
WARN_ON(1);
return -EINVAL;
}
if (!chip)
chip = &no_irq_chip;
desc = irq_desc + irq; /*Get the right IRQ descriptor */
spin_lock_irqsave(&desc->lock, flags);
irq_chip_set_defaults(chip); /* band some default handlers the to chip structure*/
desc->chip = chip; /* band the chip the right IRQ desc's chip member*/
spin_unlock_irqrestore(&desc->lock, flags);
return 0;
}
Every interrupt type has its special chip structure which defined in arm/arcm/mach--xxxx/irq.c
arch/arm/mach-s3c2410/Irq.c:
static struct irqchip s3c_irq_chip = {
.ack = s3c_irq_ack,
.mask = s3c_irq_mask,
.unmask = s3c_irq_unmask,
.set_wake = s3c_irq_wake
};
irq_chip_set_defaults
kernel/irq/Chip.c:
/*
* Fixup enable/disable function pointers
*/
void irq_chip_set_defaults(struct irq_chip *chip)
{
if (!chip->enable)
chip->enable = default_enable;
if (!chip->disable)
chip->disable = default_disable;
if (!chip->startup)
chip->startup = default_startup;
if (!chip->shutdown)
chip->shutdown = chip->disable;
if (!chip->name)
chip->name = chip->typename;
}
set_irq_handler()
include/linux/Irq.h:
static inline void
set_irq_handler(unsigned int irq,void fastcall (*handle)(unsigned int, struct irq_desc *,struct pt_regs *))
{
__set_irq_handler(irq, handle, 0);
}
kernel/irq/Chip.c:
void __set_irq_handler(unsigned int irq,void fastcall (*handle)(unsigned int, irq_desc_t *,struct pt_regs *), int is_chained)
{
struct irq_desc *desc;
unsigned long flags;
if (irq >= NR_IRQS) {
printk(KERN_ERR
"Trying to install type control for IRQ%d/n", irq);
return;
}
desc = irq_desc + irq;
if (!handle)
handle = handle_bad_irq;
if (desc->chip == &no_irq_chip) {
printk(KERN_WARNING "Trying to install %sinterrupt handler "
"for IRQ%d/n", is_chained ? "chained " : " ", irq);
/*
* Some ARM implementations install a handler for really dumb
* interrupt hardware without setting an irq_chip. This worked
* with the ARM no_irq_chip but the check in setup_irq would
* prevent us to setup the interrupt at all. Switch it to
* dummy_irq_chip for easy transition.
*/
desc->chip = &dummy_irq_chip;
}
spin_lock_irqsave(&desc->lock, flags);
/* Uninstall? */
if (handle == handle_bad_irq) {
if (desc->chip != &no_irq_chip) {
desc->chip->mask(irq);
desc->chip->ack(irq);
}
desc->status |= IRQ_DISABLED; /* if no handler, just disable this IRQ type*/
desc->depth = 1;
}
desc->handle_irq = handle;
if (handle != handle_bad_irq && is_chained) {
desc->status &= ~IRQ_DISABLED;
desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE;
desc->depth = 0;
desc->chip->unmask(irq);
}
spin_unlock_irqrestore(&desc->lock, flags);
}
set_irq_flags()
arch/arm/kernel/Irq.c:
void set_irq_flags(unsigned int irq, unsigned int iflags)
{
struct irqdesc *desc;
unsigned long flags;
if (irq >= NR_IRQS) {
printk(KERN_ERR "Trying to set irq flags for IRQ%d/n", irq);
return;
}
desc = irq_desc + irq;
spin_lock_irqsave(&desc->lock, flags);
desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
if (iflags & IRQF_VALID)
desc->status &= ~IRQ_NOREQUEST; /* clear IRQ_NOREQUEST, make the IRQ can use */
if (iflags & IRQF_PROBE)
desc->status &= ~IRQ_NOPROBE;
if (!(iflags & IRQF_NOAUTOEN))
desc->status &= ~IRQ_NOAUTOEN;
spin_unlock_irqrestore(&desc->lock, flags);
}
if desc->status get IRQ_NOREQUEST, that's meas this IRQ can't use
Register a IRQ action to a IRQ
drivers/char/watchdog/s3c2410_wdt.c:
static int
s3c2410wdt_probe(struct platform_device *pdev)
{
……
ret
= request_irq(res->start, s3c2410wdt_irq, 0, pdev->name, pdev);
……
}
and #define IRQ_WDT
S3C2410_IRQ(9)
request_irq kernel/irq/Manage.c:
/**
*
request_irq - allocate an interrupt line
*
@irq: Interrupt line to allocate
*
@handler: Function to be called when the IRQ occurs
*
@irqflags: Interrupt type flags
*
@devname: An ascii name for the claiming device
*
@dev_id: A cookie passed back to the handler function
*
*
This call allocates interrupt resources and enables the
*
interrupt line and IRQ handling. From the point this
*
call is made your handler function may be invoked. Since
*
your handler function must clear any interrupt the board
*
raises, you must take care both to initialise your hardware
*
and to set up the interrupt handler in the right order.
*
*
Dev_id must be globally unique. Normally the address of the
*
device data structure is used as the cookie. Since the handler
*
receives this value it makes sense to use it.
*
*
If your interrupt is shared you must pass a non NULL dev_id
*
as this is required when freeing the interrupt.
*
*
Flags:
*
*
IRQF_SHARED Interrupt is shared
*
IRQF_DISABLED Disable local interrupts while
processing
*
IRQF_SAMPLE_RANDOM The interrupt can be used for
entropy
*
*/
int
request_irq(unsigned int irq,
irqreturn_t
(*handler)(int, void *, struct pt_regs *),
unsigned
long irqflags, const char *devname, void *dev_id)
{
struct
irqaction *action;
int
retval;
#ifdef
CONFIG_LOCKDEP
/*
*
Lockdep wants atomic interrupt handlers:
*/
irqflags
|= SA_INTERRUPT;
#endif
/*
*
Sanity-check: shared interrupts must pass in a real dev-ID,
*
otherwise we'll have trouble later trying to figure out
*
which interrupt is which (messes up the interrupt freeing
*
logic etc).
* if SharIRQ,need different dev_id/
if
((irqflags & IRQF_SHARED) && !dev_id)
return
-EINVAL;
if
(irq >= NR_IRQS)
return
-EINVAL;
/*
clear by set_irq_flags()
in init_IRQ( )*/
if
(irq_desc[irq].status & IRQ_NOREQUEST)
return
-EINVAL;
if
(!handler)
return
-EINVAL;
/*
get a action object*/
action
= kmalloc(sizeof(struct irqaction), GFP_ATOMIC);
if
(!action)
return
-ENOMEM;
action->handler
= handler;
action->flags
= irqflags;
cpus_clear(action->mask);
action->name
= devname;
action->next
= NULL;
action->dev_id
= dev_id;
select_smp_affinity(irq);
retval
= setup_irq(irq, action);
if
(retval)
kfree(action);
return
retval;
}
And setup_irq() & __setup_irq() defined in kernel/irq/manage.c
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