Flow of fpga sim and synthesis

1. choose work server
   $telnet cadserver8$ vncserver -depth 24 -geometry 1600x900
   $ ls ~/.vnc/

2. use vnc client to access

3. work server
   $ ssh -X cadserver53-58

4. setup environment

$ source /setup/proj_dev/scr/setenv.csh

$ source /view/xxx_dview/tmp/chip/path/script/….env

1. choose the right version of RTL code
   Note: Please check if the current directory has checked out RTL code. We can issue the following command to check

$ cleartool lsco -me -cview -avobs

Then wen can edit the version of RTL code

$ cleartool edcs