S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development

San Jose, CA –Dec 16, 2025 –S2C, MachineWare, and Andes Technology today announced a collaborative co-emulation solution designed to address the increasing complexity of RISC-V-based chip design. The solution integrates MachineWare's SIM-V virtual platform, S2C's Genesis Architectand Prodigy FPGA Prototyping Systems, and Andes' high-performance AX46MPV RISC-V CPU core, providing a unified environment for hardware and software co-verification.

As RISC-V designs move toward high-performance, multi-core, and highly customized architectures, pre-silicon software development and system validation have become more challenging. This co-emulation solution supports a “shift-left” verification approach, allowing hardware and software teams to work in parallel. The result is reduced development time and lower project risk.

MachineWare's SIM-V: A High-Performance Virtual Platform

MachineWare contributes its SIM-V full-system virtual platform, based on SystemC TLM-2.0, which offers high simulation speed and extensibility. SIM-V integrates with a broad range of third-party toolchains for debugging, testing, and coverage analysis.

The key strengths of SIM-V lie in its exceptional simulation performance and comprehensive support for Andes RISC-V cores. The platform provides instruction-accurate reference models that fully implement the AndeStar V5 Instruction Set Architecture, including the RISC-V Vector (V) extension. Using the SIM-V Extension API, designers can model, validate, and debug proprietary processor enhancements within a complete system simulation, with full trace and introspection capabilities for detailed visibility. "Our customers need tools that accelerate development without compromising accuracy," said Lukas Jünger, CEO of MachineWare. "This co‑emulation solution gives them the ability to validate hardware and software in parallel, reduce integration risks, and bring products to market faster than ever before."

Andes: High-Performance, Customizable RISC-V Cores

Andes Technology contributes its advanced CPU IP, including the high-performance AndesCore™ AX46MPV multicore processor. AX46MPV is an 8-stage superscalar 64-bit RISC-V CPU that supports up to 16 cores with a multi-level cache structure, a powerful Vector Processing Unit (VPU) with up to 1024-bit VLEN and High-Bandwidth Vector Memory (HVM), and ISA customizations via Andes Custom Extension™ (ACE).

With full MMU support for Linux and versatile performance scaling, AX46MPV is well suited for data center AI computation elements, Linux-capable edge AI platforms, and high-performance MPUs in storage, networking, and other performance-critical domains.

“Our customers value our RISC-V IP for its performance, robustness, and ability to add custom extensions that accelerate their key applications.” said Dr. Charlie Su, President and CTO of Andes Technology. “By collaborating with MachineWare and S2C on this co-emulation approach, we're giving them the ability to evaluate that impact and co-optimize their software stack and silicon architecture before committing to costly silicon tapeout."

S2C: Bridging Virtual and Physical with Co-Emulation

S2C connects the SIM-V virtual platform to physical hardware through its Genesis Architect and Prodigy FPGA-based prototyping systems. In this hybrid setup, CPU models run in SIM-V while peripheral subsystems execute at high speed on FPGA, connected via a high-speed transactional bridge. This approach provides a realistic system context capable of running full software stacks—from bootloader to application—while retaining detailed debug visibility.

 

Key Use Cases & Customer Benefits

The joint solution supports multiple critical development stages:

l  Pre-silicon software development

l  Hardware/software co-verification

l  System performance analysis and tuning

l  Custom ISA extension development and debug

“Through co-emulation, our customers can accelerate time-to-market, reduce costs, and ensure software maturity—while benefiting from both cycle-accurate debugging and high-speed execution,” said Ying, VP of S2C. “But we can’t achieve this alone. We will continue to build on the high-performance advantages of hardware-assisted verification and work closely with our partners to collaboratively deliver shift-left solutions across the ecosystem.”

Looking Ahead

S2C, MachineWare, and Andes remain committed to advancing verification methodologies and providing scalable, efficient, and robust development tools for the RISC-V community. Together, the companies aim to strengthen the ecosystem for next-generation RISC-V chip design.

About MachineWare

MachineWare GmbH, headquartered in Aachen, Germany, is a leading provider of high-speed virtual prototyping solutions for pre-silicon software validation and testing. Its flagship platform, SIM‑V, delivers industry-leading RISC‑V simulation performance and extensibility, enabling accurate modeling of complex SoCs and custom ISA extensions. The company serves diverse sectors including AI, automotive, and telecommunications.

About Andes Technology

As a Founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology (TWSE: 6533[1]; SIN: US03420C2089[2]; ISIN: US03420C1099[3]) is driving the global adoption of RISC-V. Andes’ extensive RISC-V Processor IP portfolio spans from ultra-efficient 32-bit CPUs to high-performance 64-bit Out-of-Order multiprocessor coherent clusters. With advanced vector processing, DSP capabilities, the powerful Andes Automated Custom Extension (ACE) framework, end-to-end AI hardware/software stack, ISO 26262 certification with full compliance, and a robust software ecosystem, Andes unlocks the full potential of RISC-V, empowering customers to accelerate innovation across AI, automotive, communications, consumer electronics, data centers, and mobile devices. Over 17 billion Andes-powered SoCs are driving innovations globally. Discover more at www.andestech.com[4] and connect with Andes on LinkedIn[5], X (formerly Twitter)[6] , YouTube[7] and Bilibili[8].

About S2C

S2Cis a leading global supplier of FPGA prototyping solutions for today's innovative SoC and ASIC designs, now with the second largest share of the global prototyping market. S2C has been successfully delivering rapid SoC prototyping solutions since 2003. With over 600 customers, including 11 of the world's top 25 semiconductor companies, our world-class engineering team and customer-centric sales team are experts at addressing our customer's SoC and ASIC verification needs. S2C has offices and sales representatives in San Jose, Seoul, Tokyo, Shanghai, Hsinchu, India, Europe and ANZ.

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Prototyping is a crucial stage in validating SoC designs. By implementing prototyping on FPGAs, developers can begin software development and system validation long before the final hardware is ready. However, ensuring that the software developed on the pr

renzaiS2C的博客 1174

面向未来的智能视觉参考设计与汽车架构,思尔芯提供基于Arm技术的创新方案

随着科技的不断进步和市场的不断拓展,思尔芯将持续创新,并加强与全球优秀企业的生态合作,共同为新兴领域的客户提供了前沿的参考设计。作为国内数字EDA领域的先行者,思尔芯凭借其深厚的原型验证技术积累与市场实践,赢得了业界的认可。,不仅精准捕捉了当前行业发展的热点,更通过一系列实际的应用展示,为国内市场带来了切实可行的技术落地路径,也展示了思尔芯在应用级别和生态领域的投入和参与。,这是针对未来汽车多域E/E架构的创新参考设计,旨在帮助客户对新的汽车架构进行深入的探索与评估,从而为其未来的汽车设计提供有力的支持。

renzaiS2C的博客 1521

Unlocking SoC Debugging Challenges: Paving the Way for Efficient Prototyping

With the growing complexity of large-scale integrated circuits, chip verification faces immense time and cost pressures. Historically, designers relied on simulation or silicon tape-out for validation, a process that is both time-consuming and costly. Prot

renzaiS2C的博客 1150

解决验证“最后一公里”的挑战:芯神觉Claryti如何助力提升调试效率

此外,设计层次结构的查看功能能够帮助工程师更好地管理复杂的设计,Driver/Load信号的追踪功能增强了信号流向的可视化和可追踪性。通过信号追踪和分析功能,工程师可以轻松查看加载、驱动和连接的信号,支持扇入/扇出的查看,信号值的标注功能进一步提升了调试的准确性。配合设计层级的展示,覆盖率信息以结构化的方式呈现,直观展现整个设计的测试状态。与传统调试工具不同,芯神觉不仅依赖结构信息,还能推断设计行为,自动化处理复杂的调试过程,统一各种设计环境,帮助工程师理解复杂设计动态,从而大大提升调试效率。

renzaiS2C的博客 754

解锁SoC “调试”挑战,开启高效原型验证之路

特别是在大规模复杂的SoC设计原型验证过程中,工程师需要确保设计中的问题是可调试的,最大程度地减少开发过程中花费在调试上的时间。然而,对于需要进行深度调试或多FPGA级联的用户来说,常遇到的问题是需要更多内存来存储信号,以及跨FPGA的调试需求。此外,思尔芯的原型验证已内建大约10Mbps的以太网调试,支持设计中存储器映射AXI从设备的快速读写访问,可以满足低带宽的AXI调试需求。如果用户有更为特殊的需求,思尔芯还可以提供定制化的解决方案,以优化系统级的测试和调试,确保用户的原型验证过程顺利完成。

renzaiS2C的博客 1123

Why SoC Validation is Important

System-on-Chip (SoC) validation is an important part of the IC design process that tests an integrated circuit's functionality and dependability. As an IC designer, it is critical to construct complicated SoCs that can execute a variety of functions while

renzaiS2C的博客 1296
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