HDLBits从零开始——第161题到170题答案

目录

第161题：Mux

第162题：Add/sub

第163题：Case statement

第164题：Combinational circuit 1

第165题：Combinational circuit 2

第166题：Combinational circuit 3

第167题：Combinational circuit 4

第168题：Combinational circuit 5

第169题：Combinational circuit 6

第170题：Sequential circuit 7

---

第161题：Mux

module top_module 
(
    input   [1:0] sel   ,
    input   [7:0] a     ,
    input   [7:0] b     ,
    input   [7:0] c     ,
    input   [7:0] d     ,
    output  [7:0] out  
);

    wire [7:0] mux0, mux1;
    mux2 mux2_inst1 ( sel[0],    a,    b, mux0 );
    mux2 mux2_inst2 ( sel[0],    c,    d, mux1 );
    mux2 mux2_inst3 ( sel[1], mux0, mux1,  out );

endmodule

第162题：Add/sub

module top_module 
( 
    input               do_sub          ,
    input         [7:0] a               ,
    input         [7:0] b               ,
    output reg    [7:0] out             ,
    output reg          result_is_zero
);

    always @(*) begin
        case (do_sub)
          0: out = a+b;
          1: out = a-b;
        endcase

        if (out==8'b0)
            result_is_zero = 1;
        else
            result_is_zero = 0;
    end

endmodule

第163题：Case statement

module top_module 
(
    input       [7:0]   code    ,   
    output reg  [3:0]   out     ,
    output reg          valid=1 
);

     always @(*)
        case (code)
            8'h45: {out,valid} = {4'd0,1'b1};
            8'h16: {out,valid} = {4'd1,1'b1};
            8'h1e: {out,valid} = {4'd2,1'b1};
            8'h26: {out,valid} = {4'd3,1'b1};
            8'h25: {out,valid} = {4'd4,1'b1};
            8'h2e: {out,valid} = {4'd5,1'b1};
            8'h36: {out,valid} = {4'd6,1'b1};
            8'h3d: {out,valid} = {4'd7,1'b1};
            8'h3e: {out,valid} = {4'd8,1'b1};
            8'h46: {out,valid} = {4'd9,1'b1};
            default: {out,valid} = {4'd0,1'b0};
        endcase

endmodule

第164题：Combinational circuit 1

module top_module 
(
    input a,
    input b,
    output q 
);

assign q = a&b;

endmodule

第165题：Combinational circuit 2

module top_module 
(
    input   a,
    input   b,
    input   c,
    input   d,
    output  q
);

assign q = (~a & ~b & ~c & ~d)|(~a & ~b & c & d)|(~a & b & ~c & d)|(~a & b & c & ~d)
          |(a & ~b & ~c & d)|(a & ~b & c & ~d)|(a & b & ~c & ~d)|(a & b & c & d);

endmodule

第166题：Combinational circuit 3

module top_module 
(
    input   a,
    input   b,
    input   c,
    input   d,
    output  q 
);

assign q = (a|b)&(c|d);

endmodule

第167题：Combinational circuit 4

module top_module 
(
    input   a,
    input   b,
    input   c,
    input   d,
    output  q 
);

assign q = b|c;

endmodule

第168题：Combinational circuit 5

module top_module 
(
    input   [3:0] a,
    input   [3:0] b,
    input   [3:0] c,
    input   [3:0] d,
    input   [3:0] e,
    output  [3:0] q 
);

always@(*)
    case(c)
        0   :   q = b;
        1   :   q = e;
        2   :   q = a;
        3   :   q = d;
        default:q = 4'hf;
    endcase

endmodule

第169题：Combinational circuit 6

module top_module 
(
    input   [2:0]   a,
    output  [15:0]  q 
); 

always@(*)
    case(a)
        0   :   q = 16'h1232;
        1   :   q = 16'haee0;
        2   :   q = 16'h27d4;
        3   :   q = 16'h5a0e;
        4   :   q = 16'h2066;
        5   :   q = 16'h64ce;
        6   :   q = 16'hc526;
        7   :   q = 16'h2f19;
        default:q = 16'bx;
    endcase

endmodule

第170题：Sequential circuit 7

module top_module 
(
    input       clk ,
    input       a   ,
    output      q 
);

always@(posedge clk)
    q <= ~a;

endmodule