//1.
module top_module (
input in,
output out);
assign out = in;
endmodule
2.
module top_module (
output out);
assign out = 1'b0;
endmodule
3.
module top_module (
input in1,
input in2,
output out);
assign out = ~(in1 | in2);
endmodule
4.
module top_module (
input in1,
input in2,
input in3,
output out);
assign out = in3 ^ (~(in1^in2));
endmodule
5.
module top_module(
input a, b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a & b;
assign out_or = a | b;
assign out_xor = a ^ b;
assign out_nand = ~(a & b);
assign out_nor = ~(a | b);
assign out_xnor = ~(a ^ b);
assign out_anotb = a & ~b;
endmodule
5.
module top_module(
input x3,
input x2,
input x1, // three inputs
output f // one output
);
assign f = (~x3 & x2) | (x3 & x1);
endmodule
6.
module top_module (input x, input y, output z);
assign z = (x^y) &x;
endmodule
7.
module top_module ( input x, input y, output z );
assign z = ~(x^y);
endmodule
8.
module top_module(
input x,
input y,
output z);
wire o1, o2, o3, o4;
A ia1 (x, y, o1);
B ib1 (x, y, o2);
A ia2 (x, y, o3);
B ib2 (x, y, o4);
assign z = (o1 | o2) ^ (o3 & o4);
// Or you could simplify the circuit including the sub-modules:
// assign z = x|~y;
endmodule
module A (
input x,
input y,
output z);
assign z = (x^y) & x;
endmodule
module B (
input x,
input y,
output z);
assign z = ~(x^y);
endmodule
9.
module top_module(
input ring,
input vibrate_mode,
output ringer,
output motor
);
// When should ringer be on? When (phone is ringing) and (phone is not in vibrate mode)
assign ringer = ring & ~vibrate_mode;
// When should motor be on? When (phone is ringing) and (phone is in vibrate mode)
assign motor = ring & vibrate_mode;
endmodule
10.
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater = mode & too_cold;
assign aircon = !mode & too_hot;
assign fan = fan_on | heater | aircon;
endmodule
11.
module top_module(
input [2:0] in,
output [1:0] out );
assign out = in[2] + in[1] + in[0];
endmodule
12.
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );
assign out_any = in[3:1] | in[2:0];
assign out_both = in[2:0] & in[3:1];
assign out_different = in ^ {in[0], in[3:1]};
endmodule
13.
module top_module(
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different );
assign out_any = in[99:1] | in[98:0];
assign out_both = in[98:0] & in[99:1];
assign out_different = in ^ {in[0], in[99:1]};
endmodule
多路复用器
1.
module top_module(
input a, b, sel,
output out );
assign out = sel?b:a;
endmodule
2.
module top_module(
input [99:0] a, b,
input sel,
output [99:0] out );
assign out = sel?b:a;
endmodule
3.
module top_module(
input [15:0] a, b, c, d, e, f, g, h, i,
input [3:0] sel,
output [15:0] out );
always@(*)begin
case(sel)
4'd0: out = a;
4'd1: out = b;
4'd2: out = c;
4'd3: out = d;
4'd4: out = e;
4'd5: out = f;
4'd6: out = g;
4'd7: out = h;
4'd8: out = i;
default:out = 16'hffff;
endcase
end
endmodule
4.256选一复用器
module top_module(
input [255:0] in,
input [7:0] sel,
output out );
assign out = in[sel];
endmodule
5.256个4bit复用器
module top_module(
input [1023:0] in,
input [7:0] sel,
output [3:0] out );
assign out = {in[sel*4+3],in[sel*4+2],in[sel*4+1],in[sel*4+0]};
endmodule