VHDL奇分频偶分频

一、用VHDL写一个20分频程序

Entity div20 is
Port(rst,clk:in_std_logic;
		 div:out_std_logic);
end div20;
Architecture behavior of div20 is
signal cnt10:std_logic_vector(3 downto 0);
signal divt:std_logic;
begin
process(clk,rst)
begin
if rst='0' then
	cnt10<="0000";
	divt<='0';
elsif rising_edge(clk) then
	if cnt10=9 then
		divt<=not divt;
		cnt10<="0000";
	else
		cnt10<=cnt10+1;
	end if;
end if;
end process;
div<=divt;
end behavior;
--如有错误，望指出;

二、用VHDL写一个15分频

Entity div15 is
Port(clk,rst:in std_logic;
		 div:out std_logic);
end div15;
Architecture behavior of div15 is
signal cnt15:std_logic_vector(3 downto 0);
signal clk1,clk2:std_logic;
begin
process(clk,rst)
begin
if rst='0' then
	cnt15<="0000";
	clk1<='0';
elsif rising_edge(clk) then
	if cnt15=14 then
		cnt15<="0000";
		clk1<=not clk1;
	else
		cnt15<=cnt15+1;
	end if;
end if;
end process;

process(clk,rst)
begin
if rst='0' then
	clk2<='0';
elsif falling_edge(clk) then
	if cnt15=7 then
		clk2<=not clk2;
	end if;
end if;
end process;
div<=clk1 xor clk2;
end behavior;
--上述代码如有不理解的地方，可留言。
--如有错，望指出。