AHB_SRAM UVM验证（3）完善interface以及transaction

最新推荐文章于 2024-07-08 10:58:36 发布

一个玉米棒

最新推荐文章于 2024-07-08 10:58:36 发布

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完善interface以及transaction

在上一节以及搭建好了整个uvm的验证环境，添加了base的test以及base的virtual sequence。

完善lvc_ahb_if：定义的信号与dut的接口信号一致。下方的时钟块是为了与组件匹配，确定信号的传输方向。master与slave的驱动方向相反。是为了驱动和采集interface的信号。对于monitor而言，需要采集所有的信号。

`ifndef LVC_AHB_IF_SV
`define LVC_AHB_IF_SV
 
interface lvc_ahb_if;
`include "lvc_ahb_defines.svh"
import lvc_ahb_pkg::*;

	logic 									hclk;
	logic    								hresetn;	
	logic 									hgrant;	
	logic [(`LVC_AHB_MAX_DATA_WIDTH-1):0]	hrdata;
	logic 									hready;
	logic [1:0] 							hresp;
	logic [(`LVC_AHB_MAX_ADDR_WIDTH-1):0]	haddr;
	logic [2:0] 							hburst;
	logic 									hbusreq;
	logic 									hlock;
	logic [3:0] 							hprot;
	logic [2:0] 							hsize;
	logic [1:0] 							htrans;
	logic [(`LVC_AHB_MAX_DATA_WIDTH-1):0]	hwdata;
	logic 									hwrite;

	// debug 
	response_type_enum       debug_hresp;
	trans_type_enum          debug_htrans;
	burst_size_enum 		 debug_size;
	burst_type_enum 		 debug_hburst;
	xact_type_enum 			 debug_xact;
	status_enum 			 debug_status;


	// debug signals assignment
	assign debug_hresp    = response_type_enum'(hresp);
	assign debug_htrans   = trans_type_enum'(htrans);
	assign debug_hsize    = burst_size_enum'(hsize);
	assign debug_hburst   = burst_type_enum'(hburst);
	// the below signals to be assigned by monitor
	// debug_xact ..
	// debug_status ..


	// clk block
	clocking cb_mst @(posedge hclk);
	// USER: Add clocking block detail
		default input #1ps output #1ps;
		output haddr, hburst, hbusreq, hlock, hprot, hsize, htrans, hwdata, hwrite;
		input  hready, hgrant, hrdata, hresp;
	endclocking : cb_mst

	clocking cb_slv @(posedge hclk);
	// USER: Add clocking block detail
		default input #1ps output #1ps;
		input   haddr, hburst, hbusreq, hlock, hprot, hsize,<