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二维DCT的Verilog实现，包含算法基础，模块设计等所需知识。The application note describes a 2 dimensional DCT function implemented on a Xilinx FPGA. Behavioral code is provided for the implementation on any Xilinx device. Some of the advantageous of the module includes parametrizeability and performance guarantee. The code can be further optimized by instantiating embedded adders and multipliers when targeting Virtex2 family. After an initial latency of 92 clock cycles, one DCT value is output at every clock.