数字电路基础元件——VHDL代码

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#数字电路 #计数器 #分频器 #数码管

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本文介绍了使用VHDL进行数字电子基础元件设计的方法，包括计数器、数码管译码器、分频器及延时按键消抖电路的设计实现。通过具体的VHDL代码示例，展示了如何构建这些基本的数字电路组件。

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数电基础元件VHDL代码

计数器
数码管译码器
分频器
延时按键消抖

计数器

library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Counter8421 IS
	PORT(clk,rst :IN STD_LOGIC;
		cnt:OUT STD_LOGIC_VECTOR(3 downto 0);
		cout:OUT STD_LOGIC);
END Counter8421;

ARCHITECTURE count of Counter8421 IS
	signal num:STD_LOGIC_VECTOR(3 downto 0);
begin 
	process(clk,rst)
	begin
		if rst ='1' then
			num<="0000";
		elsif(clk'event and clk='1')then
			if (num = "1001") then 
				num <= "0000";
				cout<='1';
			else 
				num <= num+1;
				cout<='0';
			end if;
		end if;
	end process;
	cnt<=num;
end;

数码管译码器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY count IS 
	PORT (clk,rst:IN STD_LOGIC;
		disnum:OUT STD_LOGIC_VECTOR(6 downto 0));
END count;

ARCHITECTURE fre_div_10 of count is
signal tmp:integer range 0 to 4;
signal tmpclk:std_logic;
begin

p1:	process(rst,clk)
	begin
		if (rst='1') then tmp<=0;
		elsif (clk'event and clk='1') then
			if(tmp=4) then tmp<=0;
			else tmp<=tmp+1;
			end if;
		end if;
	end process;

p2:process(tmp)
	begin
		case (tmp) is
			when 0 =>		disnum<="1111110";
			when 1 =>		disnum<="0110000";
			when 2 =>		disnum<="1101101";
			when 3 =>		disnum<="1111001";
			when 4 =>		disnum<="0110011";
			when others =>  disnum<="0000000"; 
		end case;
	end process;
	
end fre_div_10;

分频器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Fre_Div_010 is
	port(
		clk:in std_logic;
		clk_out:out std_logic);
	end Fre_Div_010;
	
architecture a of Fre_Div_010 is
	signal tmp: integer range 0 to 4;
	signal clktmp: std_logic;
	
begin
	process (clk)
	begin
		if clk'event and clk = '1' then
			if tmp = 4 then
			tmp<=0;clktmp<= not clktmp;
				else
				tmp<=tmp+1;
				end if;
			end if;
	end process;
	clk_out<=clktmp;
end a;

延时按键消抖

library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY key_in_0 IS
	PORT(clk,kin:in std_logic;
	kout:out std_logic);
END key_in_0;

ARCHITECTURE scan_key OF key_in_0 IS
	SIGNAL a:std_logic;
	SIGNAL count:integer range 0 to 9;
BEGIN
	PROCESS(clk)
	BEGIN
		IF kin='1' THEN
			count<=0;
			ELSIF(clk' event and clk='1')
			THEN
				IF count=5 THEN count<=count;
					ELSE count<=count+1;
				END IF;
		END IF;
		IF count=4
			THEN a<='0';
			ELSE a<='1';
		END IF;
	END PROCESS;
	kout<=a;
END scan_key;