Reset and reset sequence

有如下三种复位方式:

reset Typecomment
Power on Resetreset everything: processor + debug component+Peripherals
Processor Resetreset processor only
System Resetreset processer + Perpherals

上电复位后,硬件会自动去读内存开始(内存最开始存放的是中断向量表)的前俩个数据,中断向量表前俩个如下如下:

Vector_table_0: 存放MSP的初始化指针的值
Vector_table_1: 存放Reset_handler的函数指针

然后processor会把MSP初始化指针的值赋值非MSP指针,并把Reset_handler的函数指针赋值给PC指针。所以processor是从Reset_handler这个函数开始运行的。

在这里插入图片描述

Notice:
在Crotex-M 系列处理器中,为指示使用的Thumb指令集,中断向量表中的地址的的值的LSB位的值始终是设置为1.
在这里插入图片描述
该图中中断向量表中Reset_handler的函数地址为0x101,但是函数执行的实际地址是0x100.

Reset_hanlder功能
{
1 设置MSP,可以再次设置MSP的值,比如使用外部RAM存放堆栈。
2 初始化数据段,bss段
3 重定位中断向量表
4 调用main函数
}

### QPLL Reset in FPGA or Communication Systems Explanation and Solution #### Understanding the Role of QPLL Reset In high-speed transceivers, such as those found within GTX/GTH components on FPGAs like xc7z030ffg676-2, ensuring proper initialization is critical for reliable operation at speeds up to 10.3125 Gb/s[^3]. The Quad PLL (QPLL) plays a significant role in providing stable clocking solutions necessary for these operations. Each GTX/GTH quad contains three dedicated ports specifically designed for resetting the QPLL: `QPLLRESET`, which serves as an input signal that triggers the reset process; and `QPLLLOCK`, acting as an output indicating when this procedure has successfully completed[^2]. #### Implementation Details To perform a successful QPLL reset: When initiating a system startup sequence involving GT transceivers utilizing QPLLs, it's essential first to assert the `QPLLRESET` line low before applying any other configuration settings. This action ensures all internal states are cleared properly prior to beginning normal functioning modes. Once initiated by setting `QPLLRESET=0`, wait until observing `QPLLLOCK`=high after releasing (`QPLLRESET`=1). Only proceed with further configurations once confirmation through `QPLLLOCK` status indicates stability post-reset completion. ```verilog // Example Verilog code snippet demonstrating how one might handle QPLL reset logic. initial begin // Assert reset initially qpllreset = 0; @(posedge clk); // Wait for rising edge of reference clock // Release reset and monitor lock status qpllreset = 1; while (!qpllock) @ (posedge clk); end ``` This approach guarantees synchronization between hardware elements involved during power-up sequences where timing-sensitive actions must occur sequentially without interference from previous operational remnants present inside registers or latches associated with the phase-locked loop circuitry. #### Common Issues and Solutions Failure scenarios related to improper handling of QPLL resets often manifest themselves via unstable link connections characterized by frequent retransmissions due to corrupted data frames over Ethernet interfaces operating near maximum throughput capacities supported by underlying physical layers configured using GTX transmitters/receivers set at higher baud rates exceeding typical CPLL limitations around ~5.9 GHz boundary points specified earlier. For troubleshooting purposes, consider verifying correct implementation details concerning assertion/deassertion timings applied against control lines responsible for managing state transitions throughout various stages comprising full-scale initialization routines executed upon device bootstrapping events triggered either manually under laboratory conditions or automatically following unexpected shutdown occurrences experienced out-in-the-field deployments relying heavily upon robustness provided by well-engineered recovery mechanisms built into modern-day programmable devices incorporating advanced serdes architectures optimized towards delivering superior performance metrics across diverse application domains spanning telecommunications infrastructure projects alongside enterprise networking equipment installations requiring deterministic latency characteristics along with minimal jitter levels achievable only through precise management practices adhered strictly according to manufacturer guidelines outlined within technical documentation accompanying specific product families targeted toward professional engineers working within relevant industries leveraging cutting-edge technologies offered today’s marketplace leaders specializing semiconductor fabrication processes yielding highly integrated circuits capable supporting multi-gigabit per second transfers reliably day-after-day year-over-year consistently meeting stringent quality assurance standards expected top-tier customers worldwide seeking best-of-breed solutions addressing their most challenging problems effectively yet efficiently balancing cost versus benefit tradeoffs inherent complex electronic designs pushing boundaries what currently possible given existing constraints imposed both physics materials science fields driving innovation forward continuously evolving landscape shaped rapidly advancing research efforts uncovering new possibilities previously thought unattainable just few short years ago but now becoming reality thanks relentless pursuit excellence demonstrated countless innovators contributing meaningful advancements benefiting society large scale transformative impacts felt far beyond initial conception phases eventually leading widespread adoption mainstream applications impacting everyday lives positively profound ways unimaginable decades past. --related questions-- 1. What are common pitfalls encountered during GTX/GTH transceiver initialization? 2. How does selecting between CPLL vs QPLL impact design choices for different speed requirements? 3. Can you provide examples of situations where incorrect QPLL reset leads to functional issues? 4. Are there alternative methods besides software-controlled resets for initializing QPLL? 5. In what scenarios would someone choose not to use QPLL despite its advantages?
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