systemverilog 随机约束outside 实现方法

 sv 随机约束 outside 可通过对inside 约束取反实现。示例如下：

module test_random;
    class randomize_test;
       rand bit [6:0] b;
       rand bit [5:0] e;
    
       constraint c_range{
        !(b inside {[4:20]});
        !(e inside {[63:127]});    
       }
    endclass
    
    initial begin
       randomize_test rand_test;
       for(int i=0; i<10; i++) begin
          rand_test=new();
          rand_test.randomzie();
          $dispaly("b is %0d, e is %0d", rand_test.b, rand_test.e);
       end
     end

endmodule

打印结果：

b is 86, e is 12
b is 127, e is 48
b is 114, e is 51
b is 127, e is 36
b is 103, e is 34
b is 2, e is 37
b is 67, e is 56
b is 94, e is 47 b
is 93, e is 7
b is 87, e is 53