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原创 ATF(Arm Trusted Firmware)/TF-A Chapter 05 BL2

写在最前二级boot的实现方案有很多,比如bl2,u-boot、uboot-spl, uefi。5.1. 正文开始在前一阶段,主CPU核运行bl1代码。在Bl2上,同样只有主cpu核运行bl2代码(通过platform_is_primary_cpu()函数识别主cpu核)。Bl1将系统的控制权交给bl2(跳转到BL2_BASE)。Bl2调用plat_get_bl_image_load_info()从外部flash获取要加载的image list(通过plat_get_bl_image_lo.

2021-02-05 16:23:24 3113

原创 ATF(Arm Trusted Firmware)/TF-A Chapter 04 Authentication Framework

4.1. 代码分析首先,重新分析之前忽略掉的 TRUSTED_BOARD_BOOT =1 的情况,bl1_platform_setup->arm_bl1_platform_setup->arm_load_tb_fw_config.看138行,load_auth_image会调用load_auth_image_internal:此时会执行236行宏控制的代...

2020-04-13 14:03:47 1446

原创 ATF(Arm Trusted Firmware)/TF-A Chapter 03 Chain of Trust (CoT)

本章主要介绍ATF中出现的CoT证书链和相关概念。1. 密钥和信任链概念参考和引用:Trusted Board Boot Requirements (TBBR) specification, Arm DEN0006C-1信任链(CoT)组件,在Arm开发平台上,这些组件是:信任根公钥(ROTPK)的SHA-256。 它存储在受信的根密钥存储寄存器中。 BL1镜像,假设它...

2020-04-09 17:08:09 2910

原创 ATF(Arm Trusted Firmware)/TF-A Chapter 02 BL1-ROMCode - Continued(2)

继续BL1-ROMCode 的说明。我们看下firmware desgin对BL2 load and execute的描述:In the normal boot flow, BL1 execution continues as follows:BL1 prints the following string from the primary CPU to indicate su...

2019-10-18 11:29:10 1904

原创 ATF(Arm Trusted Firmware)/TF-A Chapter 02 BL1-ROMCode - Continued(1)

先看porting guide的描述:大意是在 MMU 和d-cache disabled的情况下执行(前面分析过i-cache已经开了),并且仅由主CPU调用。功能: 启用SP805[S1]的安全实例作为可信monitor程序。 初始化UART(PL011[S2]控制台),在BL1中使用printf。 允许向与包括主CPU的cluster相对应的CC...

2019-04-05 00:39:46 2577

原创 ATF(Arm Trusted Firmware)/TF-A Chapter 02 BL1-ROMCode

2. BL12.1 Build bl1export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-Make PLAT=fvp COLD_BOOT_SINGLE_CPU=1 SPD=tspd bl1变量:COLD_BOOT_SINGLE_CPU=1 复位时只release一个core,HW设计时确定...

2018-12-17 13:58:54 5099

原创 ATF(Arm Trusted Firmware)/TF-A Chapter 01. 介绍

1.TF-A 介绍TF-A是一套通用的软件架构+特定于平台的实现代码。TF-A满足大多数SoC厂商的CPU设计:单核启动,多核启动,自定义reset vector,可裁剪的启动阶段,bootrom多平台支持,SCP-AP通讯,COT,FW update, all in one package,factory test等等。SoC厂商需要理解ARM的firmware design,并根据...

2018-12-17 11:24:43 7860

POS PED PCI 文档

The requirements set forth in this document are the minimum acceptable criteria for the Payment Card Industry (PCI). The PCI has defined these requirements using a risk-reduction methodology that identifies the associated benefit when measured against acceptable costs to design and manufacture PIN entry devices (PEDs). Thus, the requirements are not intended to eliminate the possibility of fraud, but to reduce its likelihood and limit its consequences.

2010-04-08

mips32 4ksd内核软件用户手册

mips 的 4ksd芯片手册 Unpublished work (C) MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved under the copyright laws of the United States of America and other countries. This document contains information that is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies")andmaybedisclosedonlyaspermittedinwritingbyMIPSTechnologiesoranauthorizedthirdparty. Any copying, reproducing, modifying, use or disclosure of this information (in whole or in part) that is not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly prohibited. At a minimum, this information is protected under trade secret, unfair competition and copyright laws. Violations thereof may result in criminal penalties and fines. Anydocumentprovidedinsourceformat(i.e.,inamodifiableformsuchasinFrameMakerorMicrosoftWordformat) is subject to use and distribution restrictions that are independent of and supplemental to any and all confidentiality restrictions. UNDER NO CIRCUMSTANCES MAY A DOCUMENT PROVIDED IN SOURCE FORMAT BE DISTRIBUTEDTOATHIRDPARTYINSOURCEFORMATWITHOUTTHEEXPRESSWRITTENPERMISSION OF MIPS TECHNOLOGIES, INC. MIPSTechnologiesreservestherighttochangetheinformationcontainedinthisdocumenttoimprovefunction,design orotherwise. MIPSTechnologiesdoesnotassumeanyliabilityarisingoutoftheapplicationoruseofthisinformation, or of any error or omission in such information. Any warranties, whether express, statutory, implied or otherwise, includingbutnotlimitedtotheimpliedwarrantiesofmerchantabilityorfitnessforaparticularpurpose,areexcluded. ExceptasexpresslyprovidedinanywrittenlicenseagreementfromMIPSTechnologiesoranauthorizedthirdparty,the furnishingofthisdocumentdoesnotgiverecipientanylicensetoanyintellectualpropertyrights,includinganypatent rights, that cover the information in this document. The information contained in this document shall not be exported or transferred for the purpose of reexporting in violation of any U.S. or non-U.S. regulation, treaty, Executive Order, law, statute, amendment or supplement thereto. TheinformationcontainedinthisdocumentmayonlybedisclosedtotheUnitedStatesgovernment("Government"),or toGovernmentusers,withpriorwrittenconsentfromMIPSTechnologiesoranauthorizedthirdparty. Theinformation contained in this document constitutes one or more of the following: commercial computer software, commercial computer software documentation or other commercial items. If the user of this information, or any related documentationofanykind,includingrelatedtechnicaldataormanuals,isanagency,department,orotherentityofthe Government,theuse,duplication,reproduction,release,modification,disclosure,ortransferofthisinformation,orany related documentation of any kind, is restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of this information by the Government is further restricted in accordance with the terms of the license agreement(s) and/or applicablecontracttermsandconditionscoveringthisinformationfromMIPSTechnologiesoranauthorizedthirdparty. MIPS,R3000,R4000,R5000andR10000areamongtheregisteredtrademarksofMIPSTechnologies,Inc.intheUnited Statesandothercountries,andMIPS16,MIPS16e,MIPS32,MIPS64,MIPS-3D,MIPS-based,MIPSI,MIPSII,MIPS III,MIPSIV,MIPSV,MIPSsim,SmartMIPS,MIPSTechnologieslogo,4K,4Kc,4Km,4Kp,4KE,4KEc,4KEm,4KEp, 4KS, 4KSc, 4KSd, M4K, 5K, 5Kc, 5Kf, 20Kc, 25Kf, ASMACRO, ATLAS, At the Core of the User Experience., BusBridge, CoreFPGA, CoreLV, EC, JALGO, MALTA, MDMX, MGB, PDtrace, Pipeline, Pro, Pro Series, SEAD, SEAD-2, SOC-it and YAMON are among the trademarks of MIPS Technologies, Inc.

2009-05-06

MIPS32(TM) 4KSd(TM) USIP Professional文档

This document contains confidential information that is the strict property of Innova Card, and may only be disclosed with written permission from Innova Card itself. Any copy, reproduction, modification, use or disclosure of all or part of this document, if not expressly authorized by Innova Card, is prohibited. This information is protected under trade secret, unfair competition and copying laws. This information has been provided under a Non Disclosure Agreement. Violations thereof may result in legal pursuits and fines. Innova Card reserves the right to change the information contained in this document to improve design, description or otherwise. Innova Card does not assume any liability arising from the use or application of this information, or of any error or omission of such information. Except as expressly provided by Innova Card in a written licence agreement, the availability of this document does not give the recipient licence to any intellectual property rights, including any patent rights covering the information in this document. (R) USIP is a trademark and property of Innova Card. All other trademarks referred to in this document are the property of their respective owners. Copyright (C) 2002-2006 Innova Card. All rights reserved. Do not disclose.

2009-05-06

ARM7-功能函数c代码

ARM7-功能函数c代码 1.GPIO输出实验-蜂鸣器控制 2.GPIO输出实验-单路LED控制 3.GPIO输出实验-流水灯实验。。。

2009-05-06

嵌入式拼音输入法c代码

拼音输入法C代码,在51上的实现,比较简单的C语言代码~

2010-03-20

日本c语言一级能力测验编程题和源代码

第二版 C言語プログラミング能力認定試験 1級実技試験 テーマプログラム 1.要求仕様書 2.システム仕様書 3.ソースプログラムリスト

2008-12-16

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