Note_20140805——Memory Read/Write timing cycles

最新推荐文章于 2024-12-21 12:29:19 发布

peterfeng2009

最新推荐文章于 2024-12-21 12:29:19 发布

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本文主要探讨了内存读写周期中的关键参数，如访问时间、读恢复时间和写恢复时间。内存读周期开始于地址输入，期间地址必须保持稳定，数据输出在一定延迟后变为有效。读写周期时间由访问时间、读恢复时间和写恢复时间组成。写周期则涉及到地址设置时间、写脉冲宽度等，整个过程中数据输入需保持稳定。需要注意的是，这些时间是设备本身的最小要求，实际系统的访问和周期时间会因I/O控制逻辑、系统总线逻辑和内存接口逻辑的延迟而变得更长。

OK. As you have know, all the materials is just my own note. Hopefully, you could find something interesting to you.

好的模块划分可以使得设计优化更加容易，调试的时候也更加哟利于问题的定位。

Memory Read/Write timing cycles

The most important timing parameter to be considered in choosing a memory device is the access time. The maximum time delay from an address input to a data output is longer than the delay between a chip enable and a data output, and consequently the former timing figure is normally considered to be the access time. The access time for commonly used RAMs varies from 50 to 500 ns.

For a read operation, once the output data are valid, the address input cannot be changed immediately to start another read operation. This is because the device needs a certain amount of time, called read recovery time, to complete its internal operations before the next memory operation. The sum of the access time and read recovery time is the memory read cycle time. This is the time needed between the start of a read operation and the start of the next memory cycle.

The memory write cycle time can be similarly defined and may be different from the read cycle time. The Figure below illustrates the timing of a memory read cycle. The address is applied at point A, which is the beginning of the read cycle, and must be held stable during the entire cycle. In order to reduce the access time, the chip enable input should be applied before point B. The data output becomes valid after point C and remains valid as long as the address and chip enable inputs hold.

The R/W control input is not shown in the timing diagram for the read cycle, but should remain high throughout the entire cycle.

A typical write cycle is shown in Figure above. In addition to the address and chip enable inputs, an active low write pulse on the R/W line and the data to be stored must be applied during the write cvcle. The timing of data input is less restrictive and can be satisfied simply by holding the data input stable during the entire cycle. However, the application of the write pulse has two critical timing parameters: the address setup time and the write pulse width. The address setup time is the time required for the address to stabilize and is the time that must elapse before the write pulse can be applied.

In the Figure above, the address setup time is the time interval between points A and B. The write pulse width defines the amount of time that the write input must remain active low. The write cycle time is the time interval between points A and D and is the sum of address setup time, write pulse width, and write recovery time.

It is important to note that the access time and cycle time discussed in this section are the minimum timing requirements for the memory devices themselves. The access time and cycle time for the memory system as a whole are considerably longer because of the delays resulting from the I/O control logic, system bus logic, and memory interface logic.