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最新推荐文章于 2025-08-19 12:01:54 发布

原创最新推荐文章于 2025-08-19 12:01:54 发布 · 343 阅读

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本文探讨了如何通过模拟设计技术缩小并加速记忆处理。详细介绍了不同类型的内存，包括读写内存、非易失性读写内存、只读内存等，并对比了随机访问内存、串行访问内存和内容访问内存的特点。着重阐述了易失性内存的数据丢失问题，以及RAM、ROM和NVRAM等随机访问内存的具体应用。深入分析了RAM的特性，如独立于数据物理位置的访问时间，以及ROM和RAM的进一步细分。最后，提出了低功率ROM架构的几种优化策略，如分层字线、选择性预充电和最小化非零项等。

4:03 pm

Memories can be made smaller and faster by taking advantage of analog design technique.

Types of memory (by read-write operation)

-Read-wirte memory

-Non-volatile read-write memory, read mostly memory

-Read-only memory

Types of memory (by accessing time)

-Random access memory

-Serial access memory

-Content access memory

Volatile memory-----Data is lost when supply voltage is turned off.

RAM is not a very representative acronym bcs. ROM & NVRAM are also random access memories.

RAM(Random access memory) that has an access time independent of the physical location of the data; contrasted with seria-access memories, which have some latency associated with the reading or writing of a particular datum and with content-addressable memories.

Read only memory(ROM) or Read/Write memory (RAM) are random access memory. The ROM can be further divided into static-load, synchronous, and asynchronous. Synchronous RAMs or ROMs require a clock edge to enable operation. The address to a synchronous memory only needs to be valid for a certain setup time after the clock edge.

The memory cells used in RAMs can further be divided into static and dynamic structures. Static structures used some forms of latched storage while dynamic structure use dynamic charge on a capacitor as storage.

For the low power ROM Architecture

1. Hierarchical word line

Divide the memory in different block

Only the bit cells of the desired block are accessed

2. Selective pre-charge

Only bit lines which will be accessed are pre-charged.

3. Minimization of Non-zero Terms

Zero terms do not switch bit lines and reduce the capacitance in both the bit lines and the row lines

Inverted Rom: Inverted the ROM core so that the number of one is reduced.

Inverted row: a given row is inverted if more than half of the bit s are non-zero terms.

Additional bit to indicate whether the row is inverted.