Constraints Example for Synthesis

#-------------------------------------------------------------------

# Design entry

analyze -format verilog sub1.v

analyze -format verilog sub2.v

analyze -format verilog top_block.v

eleborate top_block

current_design top_block

uniquify

check_design

#-------------------------------------------------------------------

# Setup operating conditions, wireload.clocks,resets

set_wire_load_model large_wl

set_wire_load_mode enclosed

set_operating_conditions WORST

create_clock -period 40 -waveform [list 0 20] CLK

set_clock_latency 2.0 [get_clocks CLK]

set_clock_uncertainty -setup 1.0 -hold 0.05 [get_clocks CLK]

set_dont_touch_network [list CLK RESET]

#-------------------------------------------------------------------

# Input dirives

set_driving_cell -cel [get_lib_cell buff3] -pin Z [all_inputs]

set_drive - [list CLK RST]

#-------------------------------------------------------------------

# Output loads

set_load 0.5 [all_outputs]

#-------------------------------------------------------------------

# Set input&output delays

set_input_delay 10.0 -clock CLK [all_inputs]

set_input_delay -max 19.0 -clock CLK {IN1 IN2}

set_input_delay -min -2.0 -clock CLK IN3

set_output_delay 10.0 -clock CLK [all_outputs]

#-------------------------------------------------------------------

# Advanced constraints

group_path -from IN4 -to OUT2 -name grp1

set_false_path -from IN5 -to sub1/dat_reg*/*

set_multicycle_path 2 -from sub1/addr_reg/CP \

                                      -to sub2/mem_reg/D

#-------------------------------------------------------------------

#Compile amd write the database

compile

current_design top_block

write -hierarchy -output top_block.db

write -formate verilog -hierarchy -output top_block.sv

#-------------------------------------------------------------------

# Create reports

report_timing -nworst 50

report_area