intel 公司的 815E 的资料

Intel® 815E Chipset Platform
Design Guide Update - NDA
August 18, 2000
Revision 1.1
INTEL CONFIDENTIAL
Notice: The Intel® 815E Chipset may contain design defects or errors known as errata which may
cause the product to deviate from published specifications. Current characterized errata are
documented in the Specification Update.
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Order Number: NDA DOCUMENT
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property
rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and
Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® 82815E Chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling
1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
*Third-party brands and names are the property of their respective owners.
Copyright © Intel Corporation 1999, 2000.
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Design Guide Update Intel Confidential 3
Contents
Revision History.................................................................................................................................................. 4
Preface ............................................................................................................................................................... 5
General Design Considerations.......................................................................................................................... 6
Schematic, Layout and Routing Updates ............................................................................................................ 7
Documentation Changes .................................................................................................................................. 11
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Revision History
Rev. Draft/Changes Date
1.0 Initial Release July 2000
1.1 (1) Added Documentation Change #4: Replace the GMCH Checklist 13.3.3,
DVO Port Checklist, (2) Added Document Change #5: Change the
VCORE_DET (E21) checklist item in the Miscellaneous Checklist for 370-Pin
Socket Processors 13.2.4, (3) Added Schematic, Layout and Routing Update
#2: Change schematic page 4 of 42, VCOREDET pin.
August 18 2000
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Preface
This document is an update to the specifications contained in the Intel® 815E Chipset Platform Design Guide Rev
1.0, June 2000, order number 298234-001.
References may also be made to the following documents: the Intel® 815E Chipset: Intel® 82815 Graphics and
Memory Controller Hub data sheet, June 2000, order number 290688-001, and the Intel® 82801BA (ICH) I/O
Controller Hub data sheet, June 2000, order number 290687-001.
It is intended for hardware system manufacturers and software developers of applications, operating systems, or
tools. This design guide is primarily targeted at the PC market segment and was first published in 1999. Those using
this design guide should check for device availability before designing in any of the components included in this
document
Nomenclature
General Design Considerations includes system level considerations that the system designer should account
for when developing hardware or software products using the Intel® 815E Chipset.
Schematic, Layout and Routing Updates include suggested changes to the current published schematics or
layout, including typos, errors, or omissions from the current published documents.
Documentation Changes include suggested changes to the current published design guide not including the
above.
Codes Used in Summary Table
Doc: Document change or update that will be implemented.
Shaded: This item is either new or modified from the previous version of the
document.
NO. Plans GENERAL DESIGN CONSIDERATIONS
There are no known General Design Considerations updates at this time
NO. Plans SCHEMATIC, LAYOUT AND ROUTING UPDATES
1 Doc New layout guidelines for SDRAM and SCLK and GMCH HCLK
2 Doc Change schematic page 4 of 42, VCOREDET pin
NO. Plans DOCUMENTATION CHANGES
1 Doc Update of the 3rd party Vendor List
2 Doc Section 11.3 SRCOMP change to 40 Ohm
3 Doc Update of Section 13.8 to reflect changes from layout updates
4 Doc Replace the GMCH Checklist 13.3.3, DVO Port Checklist.
5 Doc Change the VCORE_DET (E21) checklist item in the Miscellaneous Checklist for 370-Pin
Socket Processors 13.2.4.
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General Design Considerations
There are no known general design considerations at this time.
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Schematic, Layout and Routing Updates
1. Clock routing Change to Section 11.3, Figure 75 and Table 32 Pages 141,142
Please replace Section 11.3 with the following below. These new clock guidelines are for future
designs to improve PC133 SDRAM Clock Quality.
Clock Routing Guidelines
This section presents the generic clock routing guidelines for both 2-DIMM and 3-DIMM boards. For 3-DIMM
boards, additional analysis must be performed by the motherboard designer to ensure that the clocks generated by the
external PCI clock buffer meet the PCI specifications for clock skew at the receiver, when compared with the PCI
clock at the ICH2.
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Figure 75. Clock Routing Topologies
CK815 Section 1 Section 2
Layout 1
33 Ω
Connector
CK815 Section 1 Section 2
Layout 3
33 Ω
CK815 Section 1 Section 3
33 Ω
Section 0
Processor
GMCH
CK815 Section 1 Section 2
Layout 4
33 Ω
CK815 Section 1 Section 2
Layout 2
22 Ω
Section 3
22 pF 10 pF
CK815 Section 1 Section 2
Layout 5
10 Ω
Connector
clk_routing_topo
22 pF
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Table 32. Simulated Clock Routing Solution Space
Destination Topology from
Previous Figure
Section 0
Length
Section 1
Length
Section 2
Length
Section 3
Length
SDRAM MCLK Layout 5 N/A < 0.5” A1 N/A
GMCH SCLK3 Layout 2 N/A < 0.5”=L1 A + 3.5” – L1 0.5”
Processor BCLK < 0.5”
GMCH HCLK
Layout 3 < 0.1”
<0.5”
A + 5.2” A + 8”
GMCH HUBCLK Layout 4 N/A <0.5” A + 8” N/A
ICH2 HUBCLK Layout 4 N/A <0.5” A + 8” N/A
ICH2 PCICLK Layout 4 N/A <0.5” A + 8” N/A
AGP CLK Layout 4 N/A <0.5” A + 3"
to
A + 4"
N/A
PCI down2 Layout 4 N/A <0.5” A + 8.5”
to
A + 14”
N/A
PCI slot2 Layout 1 N/A <0.5” A + 5”
to
A + 11”
NOTES:
1. Length “A” has been simulated up to 6”.
2. All PCI clocks must be within 6” of the ICH2 PCICLK route length. Routing on PCI add-in cards must be
included in this length. In the presented solution space, ICH2 PCICLK was considered to be the shortest
in the 6” trace routing range, and other clocks were adjusted from there. The system designer may choose
to alter the relationship of PCI device and slot clocks, as long as all PCI clock lengths are within 6”. Note
that the ICH2 PCICLK length is fixed to meet the skew requirements of ICH2 PCICLK to ICH2 HUBCLK
3. 22pf Load cap should be placed 0.5” from GMCH Pin.
General Clock Layout Guidelines
• All clocks should be routed 5 mils wide with 15-mil spacing to any other signals.
• It is recommended to place capacitor sites within 0.5” of the receiver of all clocks. They are
useful in system debug and AC tuning.
• Series resistor for clock guidelines: 22 Ω for GMCH SCLK and 10 Ω for SDRAM clocks.
All other clocks use 33 Ω.
• Each DIMM clock should be matched within +/- 10 mils.
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Clock Decoupling
Several general layout guidelines should be followed when laying out the power planes for the CK815 clock
generator, as follows:
• Isolate power planes to the each of the clock groups.
• Place local decoupling as close as possible to power pins, and connect with short, wide traces and copper.
• Connect pins to appropriate power plane with power vias (larger than signal vias).
• Bulk decoupling should be connected to a plane with 2 or more power vias.
• Minimize clock signal routing over plane splits.
• Do not route any signals underneath the clock generator on the component side of the board.
• An example signal via is a 14-mil finished hole with a 24-mil to 26-mil path. An example power via is an
18-mil finished hole with a 33-mil to 38-mil path. For large decoupling or power planes with large current
transients, a larger power via is recommended.
2. Change schematic page 4 of 42, VCOREDET pin
Page 4 of 42 (370-Pin Socket, Part 2) of the 82815E Customer Reference Board (CRB) Schematics show
the VCOREDET pin (lower right corner of the schematic) pulled high to VCC3_3 through a 220 Ohm
resistor and also connected to VCOREDET page 8 of 42 (GMCH Reset Straps). These connections are not
correct.
The VCOREDET pin on the 370-Pin Socket, Part 2, page 4 of 42, should be left as a no-connect.
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Documentation Changes
1. Third Party Vendor Information
Reference the Intel® 815E Chipset Platform Design Guide, dated June 2000, Order Number: 298234-001.
The following four new tables are added to Chapter 14, Third Party Vendor Information:
TMDS Transmitters
Vendors Component Contact Phone
Silicon Images SII164 John Nelson (408) 873- 3111
Texas Instrument TFP420 Greg Davis [gdavis@ti.com] (214) 480-3662
Chrontel CH7301 Chi Tai Hong [cthong@chrontel.com] (408) 544-2150
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TV Encoders
Vendors Component Contact Phone
Chrontel CH7007 /
CH7008
Chi Tai Hong
[cthong@chrontel.com]
(408)544-2150
Chrontel CH7010 /
CH7011
Chi Tai Hong
[cthong@chrontel.com]
(408)544-2150
Conexant CN870 /
CN871
Eileen Carlson
[eileen.carlson@conexant.com]
(858) 713-3203
Focus FS450 / FS451 Bill Schillhammer
[billhammer@focusinfo.com]
(978) 661-0146
Philips SAA7102A Marcus Rosin
[marcus.rosin@philips.com]
None
Texas Instrument TFP6022/
TFP6024
Greg Davis
[gdavis@ti.com]
(214) 480-3662
Combo TMDS Transmitters/TV Encoders
Vendors Component Contact Phone
Chrontel CH7009/
CH7010
Chi Tai Hong
[cthong@chrontel.com]
(408) 544-2150
Texas Instrument TFP6422/
TFP6424
Greg Davis
[gdavis@ti.com]
(214) 480-3662
LVDS Transmitter
Vendors Component Contact Phone
National
Semiconductor
387R Jason Lu
[Jason.Lu@nsc.com]
(408) 721-7540
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2. System Memory Checklist SRCOMP change: Section 13.10, the final entry in the
table should read as shown below
SRCOMP Needs a 40-Ω resistor pulled up to 3.3 V
3. Change in Checklist section 13.8
In Section 13.8, the last box changes as follows:
MEMCLK0/DRAM_0,
MEMCLK1/DRAM_1,
MEMCLK2/DRAM_2,
MEMCLK3/DRAM_3,
MEMCLK4/DRAM_4,
MEMCLK5/DRAM_5,
MEMCLK6/DRAM_6,
MEMCLK7/DRAM_7,
Pass through 10 Ω resistor
SCLK Pass through 22 Ω resistor
4. Replace Checklist Section 13.3.3, Digital Video Output Port Checklist.
Checklist Section 13.3.3, page 161, is replaced with the following:
13.3.3 Digital Video Input Checklist
Checklist Items Recommendations
DVI Input Reference Circuit See reference schematics in the documentation of the third party vendor of the
device of choice in your design. The Third Party Vendor information is a part of
this Design Guide and its associated Design Guide Updates.
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5. Change the VCORE_DET (E21) checklist item in the Miscellaneous Checklist
for 370-Pin Socket Processors 13.2.4.
Checklist section 13.2.4, page 159: Change the Recommendations section of the VCORE_DET (E21)
checklist item as follows:
VCORE_DET (E21) This pin should be left as a no-connect.

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