0×03:FPGA设计思想

再次遇到问题，再次回来看书，再次摘录了一些笔记

写Testbench

主线程：Initial
It is good design practice to partition the individual test case from the main
thread.

It is good design practice to create an automated, self-checking testbench. This
will save a significant amount of time down the road as the testbench grows.

时钟和复位：
Initialize testbench clocks and resets with nonblocking assignments and update
them with blocking assignments.

Test Cases
Create test cases such that they can stand alone inside the main thread.

Reference signals inside the design at the module boundaries whenever possible.

MATLAB can be very useful when creating large or complex patterns for simulation

Code coverage(这个类似于一个集合)
Code coverage checks the extent to which the design has been simulated and
identifies any unsimulated structures.

Gate-level simulations can be useful when estimating dynamic power dissipation.

Run-Time Traps
Timescale
Timescale precision must be chosen to balance simulation accuracy against
run-time.

关于glitch(不太理解)
Intertial delays due to combinatorial logic should be modeled with continuous
assignments

综合优化

速度VS面积

工具的的速度/面积选项不是什么时候都有用。综合级的优化取决于实现RTL时所用的拓扑结
构。
虽然FPGA速度/面积交换的基本思想是更快的电路需要更多的并行和更大的面积。但由于FPG
A布局时的二阶效应，最后的结果并非我们所期望。
这就带来一个问题，过分的面积展开使得编译器在布线完成之后才发现器件是十分的拥挤，
而工具别无选择，只能将这些器件堆砌（而不是优化）到任何合适的地方,这就拖慢了整个
系统。

As the resource utilization approaches 100%, a speed optimaization at the
synthesis level may not always produce a faster design. In fact, an area
optimization can actually result in a faster design.

结论就是须要一定的约束，但不能过约束。（cipher觉得这个要做多次实验吧）

资源共享

实际上资源共享是综合工具的工作，非关键路径都可以实现资源共享，不过：
If resource sharing is activated, veriy that it is not adding delay to the
critical path.

流水线、时序重组以及寄存器平衡

综合工具移动触发器在逻辑和寄存器间的位置，以减小延迟时间。但是：
Register balancing should not be applied to noncritical paths.

Adjacent flip-flops with different reset types may prevent register balancing
from taking place.

Constrain resychronization registers such that they are not affected by register
balancing.

关于FSM
Design state machines with standard coding styles so they can be identified and reoptimized by the synthesis tool.
FSM编码方式
One-hot :速度快，但是占用的寄存器多。
Gray码：用于异步输出（力荐，免于竞争和毛刺）、低功耗设备。

关于黑盒子

if a black box is required, include the timing models for the I/O.

关于floorplanning

By partitioning the floorplan between major functional boundaries, timing
compliance can be considered on a block-by-block basis.

when floorplanning the critical path, the floorplan is a key link in the
iterative timing closure loop.

A bad floorplan can dramatically reduce the performance of a design.

Floorplanning is a good fit for highly pipelined designs or for layouts
dominated by routing delay.

优化floorplanning
The floorplan usually includes the data path but not the associated control or
glue logic.

A floorplan should take into consideration built-in resources such as memories,
carry chains, DSPs, and so forth.

A floorplan targeted at minimizing trace lengths of high-activity nets can
reduce dynamic power dissipation.