1 OVM2.1.1 -> UVM1.0ea(early Adoption)
2 UVM1.0 2011.2 (Major EDA vendor support UVM, SNPS/VCS,Cadence/IUS,Mentor/Questa) Became a standard Verification Methodology
3 UVM 1.0EA New feature :
3.1 Objection to control End-of-Test
3.2 Callback -> ( compatible with VMM , for customizing behavior)
3.3 Report catcher for report customize
3.4 heartbeat for VC liveness monitoring.
4 UVM 1.1x New feature :
4.1 RAL From VMM RAL
4.2 Phasing : user-defined phases, user-defined relationships.
4.3 Sequence Mechanism :
4.4 TLM-2.0
4.5 Resource config .
4.6 CLP : Command line processor
5 UVM-1.2 :
5.1 uvm_sequence_base::starting phase -> set_starting_phase/get_starting_phase
5.2 uvm_sequence_base::set_automatic_phase_objection(0/1)。 avoid the need to call raise_objection()/drop_objection()
5.3 `uvm_info_begin/`uvm_info_end, uvm_report_server can be extend and customized .
5.4 uvm_recorder can be customized.
5.5 factory can be undone by explicitly to default value .
5.6 starndard factory can be overrided by user-defined factory for debug functionly.
5.7 objection propagation objection can be turned-off. uvm_objection::set_progagate_mode .
5.8 uvm_phase::get_objection_count , can be used to drop all the objections.
5.9 uvm_phase:: get_adjacent_predecessor/successor_nodes for phase schedule introspection
5.10 new call back uvm_phase_cb to allow phase callback.
5.11 class extend from uvm_object must have constructor.
5.12 uvm_event parameterized with optional event payload.
5.13 uvm_bitstream_t -> uvm_integral_t
5.14 uvm_reg_transaction_order_policy( -> specify the order of bus transactions for wide register access.
5.15 uvm_sequence_state_enum/uvm_sequencer_arb_mode