bayer2RGB

module bayer2RGB(
                input          I_rst_p,
					  input          I_clk_pixel,
                 input  [7:0]   I_bayer_data,
                 input          I_v_sync,//high active
                 input          I_h_sync,//high active -data valid
					  output [15:0]  O_RGB_data,
                output [7:0]   O_RGB_data_R,
                 output [7:0]   O_RGB_data_G,
                 output [7:0]   O_RGB_data_B,
                 output         O_RGB_data_valid,
                 output         O_v_sync
    );
parameter ROW_WIDTH = 1920;
parameter COL_WIDTH = 1080; //0325 HM

reg          v_sync_d1;
reg          v_sync_d2;
reg          v_sync_d3;
wire         v_sync_pos;
reg          h_sync_d1;
reg          h_sync_d2;
reg          h_sync_d3;
wire         h_sync_pos;
reg  [7:0]   bayer_data_d1;
reg  [7:0]   bayer_data_d2;
reg  [7:0]   bayer_data_d3;

reg  [10:0]  row_cnt;// 0-1024
reg  [10:0]   col_cnt;//0-768
wire [7:0]   shift_reg1_dout;
wire [7:0]   shift_reg2_dout;
reg  [7:0]   shift_reg2_dout_d1;

reg          RGB_data_valid;  
reg  [7:0]   RGB_R;
reg  [8:0]   RGB_G;
reg  [7:0]   RGB_B;

always@(posedge I_clk_pixel)
   begin
      v_sync_d1 <= I_v_sync;
      v_sync_d2 <= v_sync_d1;
      v_sync_d3 <= v_sync_d2;
      h_sync_d1 <= I_h_sync;
      h_sync_d2 <= h_sync_d1;
      h_sync_d3 <= h_sync_d2;                 
      bayer_data_d1 <= I_bayer_data;
      bayer_data_d2 <= bayer_data_d1;  
      bayer_data_d3 <= bayer_data_d2;  
      shift_reg2_dout_d1 <= shift_reg2_dout;
   end
assign v_sync_pos = v_sync_d1 & (~v_sync_d2);
assign h_sync_pos = (~h_sync_d1) & h_sync_d2;
//=======================================================================cnt
always@(posedge I_clk_pixel or posedge I_rst_p)
   begin
      if(I_rst_p)
         row_cnt <= 11'b0;
      else if(v_sync_pos)
         row_cnt <= 11'b0;   
      else if(h_sync_d2)
         if(row_cnt == ROW_WIDTH-1 )
            row_cnt <= 11'b0;
         else
            row_cnt <= row_cnt+ 1;
      else
          row_cnt <= row_cnt;              
   end
always@(posedge I_clk_pixel or posedge I_rst_p)
      begin
         if(I_rst_p)
            col_cnt <= 11'b0;
         else if(v_sync_pos)
            col_cnt <= 11'b0;            
         else if(row_cnt == ROW_WIDTH-1 && h_sync_d2)
             col_cnt <= col_cnt+ 1;
         else
             col_cnt <= col_cnt;              
      end  
//=================GBRG==================================
always@(posedge I_clk_pixel or posedge I_rst_p)
   begin
      if(I_rst_p)
         begin
            RGB_R <= 8'b0;
            RGB_G <= 8'b0;
            RGB_B <= 8'b0;
         end
      else
         case({col_cnt[0],row_cnt[0]})
            2'b00:
               begin
                  RGB_R <= bayer_data_d2;   //0407 调整顺序
                  RGB_G <= (bayer_data_d1 + shift_reg2_dout_d1)>>1;
                  RGB_B <= shift_reg2_dout; 
               end    
            2'b01:
               begin
                  RGB_R <= bayer_data_d1;
                  RGB_G <= (bayer_data_d2 + shift_reg2_dout)>>1;
                  RGB_B <= shift_reg2_dout_d1;
               end  
            2'b10:
               begin
                  
						RGB_R <= shift_reg2_dout_d1;
                  RGB_G <= (bayer_data_d2 + shift_reg2_dout)>>1;// 0407 HM 右移一位相当于除以2
                  RGB_B <= bayer_data_d1;
               end
            2'b11:
               begin
                  
						RGB_R <= shift_reg2_dout;
                  RGB_G <= (bayer_data_d1 + shift_reg2_dout_d1)>>1;
                  RGB_B <= bayer_data_d2;
               end                                                                
            default:
               begin
                  RGB_R <= 8'b0;
                  RGB_G <= 8'b0;
                  RGB_B <= 8'b0;
               end
         endcase
   end
shift_ram_1 u_shift_ram_1 (
  .d(bayer_data_d1),    // input wire [7 : 0] D
  .clk(I_clk_pixel),    // input wire CLK
  .ce(h_sync_d1),   // input wire CE
  .sclr(I_rst_p),   // input wire SCLR
  .q(shift_reg1_dout)   // output wire [7 : 0] Q
);

shift_ram_2 u_shift_ram_2 (
  .d(shift_reg1_dout),        // input wire [7 : 0] D
  .clk(I_clk_pixel),    // input wire CLK
  .ce(h_sync_d1),      // input wire CE
  .sclr(I_rst_p),  // input wire SCLR
  .q(shift_reg2_dout)        // output wire [7 : 0] Q
);

assign O_RGB_data_valid = h_sync_d3;
assign O_v_sync = v_sync_d3;
assign O_RGB_data = {RGB_R[7:3],RGB_G[7:2],RGB_B[7:3]} ;
assign  O_RGB_data_R = RGB_R;
assign  O_RGB_data_G = RGB_G[7:0];
assign  O_RGB_data_B = RGB_B;


endmodule