本文介绍了缓存优化的重要性，特别是针对矩阵乘法操作。通过计算2 * blockSize^2 * wordSize等于L1缓存大小，强调了缓存利用率的关键作用。文章探讨了不同级别缓存的延迟，指出为了维持高性能，必须在每一层都有高比例的缓存命中率。此外，还提及了如何通过预加载到局部变量来减少内存带宽需求，以暴露指令级并行性。
2 * (blockSize)2 * wordSize = L1 cache size.
Degrees of Latency
The latency of data access becomes greater with each cache level. Latency of memory access is best measured in CPU clock cycles. One cycle occupies from 4 to 6 nanoseconds, depending on the CPU clock speed. The latencies to the different levels of the memory hierarchy are as follows:
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CPU Register: 0 cycles.
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L1 cache hit: 2 or 3 cycles.
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L1 cache miss satisfied by L2 cache hit: 8 to 10 cycles.
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L2 cache miss satisfied from main memory, no TLB miss: 75 to 250 cycles; that is, 300 to 1100 nanoseconds, depending on the node where the memory resides (see Table 1-3).
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TLB miss requiring only reload of the TLB to refer to a virtual page already in memory: approximately 2000 cycles.
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TLB miss requiring virtual page to load from backing store: hundreds of millions of cycles; that is, tens to hundre
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