- 博客(4)
- 收藏
- 关注
RSS订阅原创 Verilog Keyword
Keywords are predefined nonescaped identifiers that define Verilog language constructs. An escaped identifier shall not be treated as a keyword.
2022-06-07 10:57:00
1890
原创 SV SystemVerilog Keywords
SystemVerilog reserves the keywords listed below:accept_onaliasalwaysalways_combalways_ffalways_latchandassertassignassumeautomaticbeforebeginbindbinsbinsofbitbreakbufbufif0bufif1bytecasecasexcasezcellchandlecheckerclassclocki
2022-05-27 14:52:37
310
原创 My First Article
Master Xunzi said that，the living place and following friends must be chosen, so that I came here to document my progress and growth.As an IC verification engineer, the skill to use English is significant. That's the reason why I want to write all the co
2022-05-06 18:43:40
243
空空如也
空空如也
TA创建的收藏夹 TA关注的收藏夹
TA关注的人