正则表达式切分module * end

import re

# 测试文本
text = """
Declare all signals as `reg` data types.
 module header:

module xor_module (
  input a,
  input b,
  output out
);

  reg out;

  assign out = (a & ~b) | (~a & b);

endmodule

You are tasked with designing a module in Verilognput. The module should lines.

The module should be defined with the following ports:

module another_module (
  input c,
  output d
);

  reg d;

  assign d = ~c;

endmodule
"""

pattern = re.compile(r"(.*?)module\s+(\w+)\s?\((.*?)\);(.*?)endmodule", re.DOTALL)

matches = re.findall(pattern, text)
for match in matches:
    print("module "+match[1]+"("+match[2]+");"+match[3]+"endmodule")
# print("匹配到的:", matches)