HDLBits自学笔记4:Verilog language.Procedures + More Verilog Features

Procedures

Always blocks(combinational)

建立一个与门，用assign语句和always语句

module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);
    assign out_assign = a & b;
    always @(*) begin
        out_alwaysblock = a & b; 
    end
endmodule

Always blocks(clocked)

建立一个异或门，使用assign语句、组合always语句和时序always语句

module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   );
    
    assign out_assign = a ^ b;
    
    always @(*) begin
       	out_always_comb = a ^ b; 
    end
    
    always @(posedge clk) begin
        out_always_ff <= a ^ b;
    end
endmodul

Always if

if语句通常用于创建2选1选择器，等同于三目运算符：assign out = (condition) ? x : y;

建立一个2选1选择器，如果sel_b1和sel_b2为真，选择b，其他情况选择a，使用assign和always

module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 
	
    assign out_assign = (sel_b1 & sel_b2) ? b : a;
    
    always @(*) begin
        if(sel_b1 & sel_b2)
            out_always = b;
        else
            out_always = a;
    end
    
endmodule

If statement latches

如下代码产生了锁存器，修复代码：

always @(*) begin
    if (cpu_overheated)
       shut_off_computer = 1;
end

always @(*) begin
    if (~arrived)
       keep_driving = ~gas_tank_empty;
end

修复后：

module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  ); //

    always @(*) begin
        if (cpu_overheated)
            shut_off_computer = 1;
        else
            shut_off_computer = 0;
    end

    always @(*) begin
        if (~arrived)
            keep_driving = ~gas_tank_empty;
        else
            keep_driving = 0;
    end

endmodule

Case statement

用case语句创建一个6选1多路选择器

module top_module ( 
    input [2:0] sel, 
    input [3:0] data0