TASKING LSL EXAMPLE FOR TRICORE TC397XP

C文件源码

/*****************************************************
 *
 * TC397XP_TST.c
 *
 * Description : Hello World in C, ANSI-style
 *
 */
#include <stdio.h>
#include <stdint.h>


/*____________________________________________________________________________*/

#pragma section all "SHT_ConstZone"

__near volatile const uint32_t CZ_CALIB_A = 0x01U;

#pragma protect on
__near volatile const uint32_t CZ_CALIB_B = 0x02U;
#pragma protect off

#pragma section all restore

/*____________________________________________________________________________*/
// use __attribute__((protect)) to exclude a variable/function from
// the duplicate/unreferenced section removal optimization in the linker.
#pragma section all "SHT_ConstPara"
__attribute__((protect)) volatile const unsigned char CP_NormalPara = 0;
#pragma section all restore


/*____________________________________________________________________________*/

#pragma section fardata "SHT_Assign_DLMU0"

#pragma section_name_with_symbol
__protect__ __far int dlmu_core0 = 0;
#pragma section_name_with_symbol off

#pragma section fardata restore

/*____________________________________________________________________________*/
#pragma  section all "SHT_Assign_NearAddr"
__protect__  __near volatile uint32_t Var_ToNearAddr;
#pragma  section all restore

/*____________________________________________________________________________*/
#pragma  section all "SHT_Assign_DLMUCPU0"
//__attribute__((protect)) volatile uint32_t LargeArray[0x4000] =  {0x1234};
__attribute__((protect)) volatile uint32_t LargeArray[0xF0] =  {0x1234};
__attribute__((protect)) volatile uint32_t BesideArray =  5555;
#pragma section all restore

/*____________________________________________________________________________*/
#pragma  section all "SHT_Assign_LMURAM2"
__attribute__((protect)) volatile uint32_t Var_In_lmuram2 =  0x1234;
#pragma section all restore

/*____________________________________________________________________________*/
__attribute__((protect)) volatile uint32_t Var_In_DefRam =  0x1884;


/*____________________________________________________________________________*/
uint16_t Glb_NmlVar;
__protect__ __near uint16_t sht_my_var;

/* Glb_ExtNmlVar defined in another application located at address 0x70001000 */
extern uint16_t Extern_NmlVar;
extern uint16_t Glb_ExtNmlVar;

/*____________________________________________________________________________*/
/* the default near allocation value is set to zero to
 * prevent any near addressable sections without using the __near qualifier */
__protect__ uint32_t glb_default_near_var = 0xAFFA5A5A;


__protect__ uint32_t glb_calib_value = 0xA5A5;
__protect__ uint32_t glb_keep_value;

/*____________________________________________________________________________*/
/* sht_void_func defined in another application located at address 0x80007000 */
void sht_extern_func(void);

void sht_init_func(void);

/*____________________________________________________________________________*/
void sht_tst1st_func(void);
void sht_tst2nd_func(void);
void sht_tst3rd_func(void);

/*____________________________________________________________________________*/
__protect__ uint8_t glb_OVTFL_arr1[0x200]; /* 0.5K */
__protect__ uint8_t glb_OVTFL_arr2[0x200]; /* 0.5K */
__protect__ uint8_t glb_OVTFL_arr3[0x200];


/*____________________________________________________________________________*/
void sht_tst1st_func(void)
{
	printf( "I'm sht_tst1st_func\n");
}
void sht_tst2nd_func(void)
{
	printf( "I'm sht_tst2nd_func\n");
}
void sht_tst3rd_func(void)
{
	printf( "I'm sht_tst3rd_func\n");
}
/*____________________________________________________________________________*/

void sht_init_func(void)
{
	Glb_NmlVar = 0x1234;
}

void sht_func_in_lmuram(void)
{
	printf( "the linker creates a copy table entry for the initialized function\n");
}

void sht_func_in_app(void)
{
	printf( "used in a copy loop executed by the application code.\n");
}

/*____________________________________________________________________________*/
/* use a linker label to determine the start address of the group in flash */
extern __far uint32_t _lc_gb_ROM_COPY_INIT_CODE;
/* use a linker label to determine the end address of the group in flash */
extern __far uint32_t _lc_ge_ROM_COPY_INIT_CODE;
/* use a linker label to determine the start address of the overlay group in RAM memory */
extern __far uint32_t _lc_gb_INIT_CODE;

void Initialize_the_RAM_function(void)
{
	/* load the start address of the ROM copy group into source pointer */
	uint32_t *source = &_lc_gb_ROM_COPY_INIT_CODE;
	/* load the start address of the RAM group into destination pointer */
	uint32_t *dest = &_lc_gb_INIT_CODE;

	/* initialize the RAM function using a copy loop */
	for(uint32_t loopcount=0; loopcount <
	(&_lc_ge_ROM_COPY_INIT_CODE-&_lc_gb_ROM_COPY_INIT_CODE); loopcount++)
	{
		*dest++ = *source++;
	}
}
/*____________________________________________________________________________*/

int main(void)
{
	uint32_t var_u32_tst = 0x00;

	Glb_ExtNmlVar = 0x03;

	printf( "Hello TASKING: %u", var_u32_tst);

	printf( "Hello world: %8u\n", CZ_CALIB_B);

	sht_init_func();
	sht_extern_func();

	Initialize_the_RAM_function();
	while(1)
	{
	    __nop();
	}
}

LSL文件测试代码

//****************************************************************************
//**                                                                         *
//**  FILE        :  cpu.lsl                                                 *
//**                                                                         *
//**  DESCRIPTION :  Project specific Linker Script.                         *
//**                                                                         *
//**  Copyright 2007-2019 TASKING BV                                         *
//**                                                                         *
//****************************************************************************

// TASKING VX-toolset for TriCore
// Eclipse project linker script file

/*____________________________________________________________________________*/

//the group name is shown in the map file when the assignment was successful
section_layout :vtc:abs18
{
	// group entry to place a non initialized far addressed data section in LMURAM memory
	group MY_DATA ( ordered, run_addr=mem:mpe:dspr0 )
	{
	   select ".zbss.TC397XP_TST.sht_my_var";
	}
}

/*____________________________________________________________________________*/
section_layout :vtc:linear
{
	/* variable Glb_ExtNmlVar is included in another project and located at address 0x70001000 */
	"Glb_ExtNmlVar" = 0x70001000;
	
	/* Can make a symbol conditional : created only when it is referenced in an object file.*/
	/* For this purpose, use ":="  */
	"Extern_NmlVar" := 0x70002000;
	
	
	/* function sht_extern_func is included in another project and located at address 0x80007000 */
	"sht_extern_func" := 0x80007000;
}

/*____________________________________________________________________________*/
section_layout mpe:vtc:abs18
{
    group MY_CAL_ZONE(contiguous,ordered, run_addr = 0x80000800)
    {                          
        select ".zrodata.SHT_ConstZone";
    }
}

/*____________________________________________________________________________*/

section_layout mpe:vtc:linear
{
    group MY_calibration(ordered, contiguous, run_addr = 0x70000100, attributes=rw, fill=0)
    {
        section "calibration_section" (size = 32, attributes=rw, fill=0)
        {
            select "*.SHT_ConstPara";
        }
    }
}
/*____________________________________________________________________________*/

section_layout mpe:vtc:linear
{
    group MY_dlmu0(ordered, contiguous, run_addr = 0x70000400, attributes=rw, fill=0)
    {
        select "*.SHT_Assign_DLMU0";
    }
}

/*____________________________________________________________________________*/
section_layout :vtc:abs18
{       
    group MY_tst_bss(ordered, run_addr=0x10000800)//
    {
        select".zbss.SHT_Assign_NearAddr";
    }
}
/*____________________________________________________________________________*/
section_layout :vtc:linear
{       
    group MY_tst_data(ordered, run_addr=mem:mpe:dlmucpu0/not_cached)
    {
        select".data.SHT_Assign_DLMUCPU0";
    }
}

/*____________________________________________________________________________*/
section_layout mpe:vtc:linear
{       
    group MY_tst_LMU_data(ordered, run_addr=mem:mpe:lmuram2)//
    {
        select".data*.SHT_Assign_LMURAM2";
    }
}
/*____________________________________________________________________________*/
section_layout mpe:vtc:linear
{       
    group MY_RAW_LMU_data(ordered, run_addr=mem:mpe:lmuram2)//
    {
        select".data.TC397XP_TST.RawVar_In_lmuram2";
    }
}
/*____________________________________________________________________________*/

section_layout mpe:vtc:linear
{       
    group MY_printf(ordered, run_addr = mem:mpe:pflash0/not_cached)//0x80000300)//
    {
        select".text.printf.libcs_fpu";
    }
}

/*____________________________________________________________________________*/
// section_setup entry for the source location (here virtual linear memory, vtc)
section_setup mpe:vtc:linear
{
	// Link time code core association private to assign the section to core0 memory
	modify input (space = mpe:tc0:linear)
	{
	   select ".text.TC397XP_TST.sht_init_func";
	}
}

// section_layout entry for the placement of the section in TC0 local PSPR0 memory
// and the 'copy' keyword for the linker to create a ROM copy section
// for the initialized code
section_layout :tc0:linear
{
	group TC0_FUNCTIONS ( ordered, run_addr=mem:mpe:pspr0, copy )
	{
	   select ".text.TC397XP_TST.sht_init_func";
	}
}

/*____________________________________________________________________________*/
section_layout :vtc:linear
{
	group SHT_Init_Area( ordered, run_addr = mem:mpe:dspr0 )
	{
		/* Define output section BSS_DATA with a size of 1kB in memory DSPR0 and
		* assign the arrays defined in TC397XP_TST.c to this section.
		* Use overflow output section BSS_DATA_OVERFLOW for sections
		* that do not fit in BSS_DATA. */
		section "BSS_DATA" (size=1k, attributes=rw, overflow = "BSS_DATA_OVERFLOW")
		{
		   select ".bss.TC397XP_TST.glb_OVTFL_arr*";
		}
	}
	group SHT_Backup_Area( ordered, run_addr = mem:mpe:dspr1 )
	{
		/* If the available space of 1kB is not enough for all sections starting
		* with the name .bss.TC397XP_TST.glb_OVTFL_arr
		* this overflow section with a size of 1 kB is used for the remaining sections. */
		section "BSS_DATA_OVERFLOW" (size=1k, attributes=rw)
		/* Instead of using a fixed absolute size for the output section you can
		* use the blocksize keyword to specify an adaptive size.
		* Then the size of the output section increases to a multiple of
		* the blocksize value. */
		/* section "BSS_DATA_OVERFLOW" (blocksize=2k, attributes=rw) */
		{
		}
	}
}
/*____________________________________________________________________________*/
section_layout :vtc:linear
{
	// generate a ROM copy section and a copy table entry for the startup code
	// in order to copy the code from ROM to RAM during startup
	group NML_INIT_CODE ( ordered, run_addr=mem:mpe:lmuram0, copy )
	{
	   select ".text.TC397XP_TST.sht_func_in_lmuram";
    }
}

/*____________________________________________________________________________*/
section_layout :vtc:linear
{
	/* generate a ROM copy section for initialized code */
	group INIT_CODE (overlay, ordered, run_addr=mem:mpe:dspr0)
	{
	   select ".text.TC397XP_TST.sht_func_in_app";
	}
	/* assign the ROM copy of the initialized section to a group to determine start and end address */
	group ROM_COPY_INIT_CODE (ordered, load_addr)
	{
	   select ".text.TC397XP_TST.sht_func_in_app";
	}
}

/*____________________________________________________________________________*/
section_layout :vtc:linear
{
	/* reserves 256B in pflash0 memory starting at offset 0x100 in this memory range */
	group ( ordered, run_addr = mem:mpe:pflash0[0x100] )
	{
	   reserved "MY_RESERVE" ( size = 256 );
	}
	
	/* reserves 256B in pflash0 memory starting at offset 0x200 in this memory range */
	/* To allow absolute-placed sections use alloc_allowed=absolute */
	group ( ordered, run_addr = mem:mpe:pflash0[0x200] )
	{
	   reserved "MY_LARGER_RESERVE" ( alloc_allowed=absolute, size = 256 );
	}
	
	/*group is placed at the absolute start address offset 0x320 in memory pflash0 which
       is within the reserved range.*/
	group SPECIAL_1ST2ND_FUN ( ordered, contiguous, run_addr = mem:mpe:pflash0[0x320] )
	{
		select ".text.TC397XP_TST.sht_tst1st_func";
		select ".text.TC397XP_TST.sht_tst2nd_func";
	}
}

/*____________________________________________________________________________*/
section_layout :vtc:linear
{
    /*To allow placement of sections which are placed in a memory range use alloc_allowed=ranged.*/
    group ( ordered, run_addr = mem:mpe:pflash1[0x200] )
    {
       reserved "MY_ANOTHER_RESERVE" ( alloc_allowed=ranged, size = 256 );
    }
    
    /*group is placed in an address range, starting at offset 0x380 and ending at offset
         0x3A0 in memory pflash1 which is within the reserved range.*/
    group SPECIAL_3RD_FUN ( ordered, contiguous, run_addr = mem:mpe:pflash1[0x380..0x3A0] )
    {
        select ".text.TC397XP_TST.sht_tst3rd_func";
    }
}


/*____________________________________________________________________________*/
/* The name of the ROM copy section is equal to the name of the RAM section,
   but the ROM copy section name is offset by square brackets [ ].
*/
section_layout :vtc:linear
{
	/* To select a ROM copy section you need to use the full name
	   including the square brackets in the select line for an LSL group. 
	   In order to have them accepted by the linker you need to escape them using "\".
	*/
	
	/* To have ROM section placed starting at offset 0x100 in pflash2 memory */
	group MY_ROM_COPY_SECTIONS ( ordered, run_addr = mem:mpe:pflash2[0x100] )
	{
	   select "\[.data.TC397XP_TST.glb_default_near_var\]";
	}
	
	/* instead of using run_addr in the group definition you can use the keyword load_addr.
     This informs the linker to select the ROM copy of initialized sections.
     When doing this, you need to remove the square brackets to select the section:
	*/
	
	/* To have ROM section placed starting at offset 0x200 in pflash2 memory */
	group MY_ROM_LOAD_SECTIONS ( ordered, load_addr = mem:mpe:pflash2[0x200] )
	{
	   select ".data.TC397XP_TST.glb_default_near_var";
	}
	
	/* To have the RAM section placed starting at offset 0x200 in DSPR2 RAM */
	group MY_INITIALIZED_SECTIONS ( ordered, run_addr = mem:mpe:dspr2[0x200] )
	{
	   select ".data.TC397XP_TST.glb_default_near_var";
	}
}

/*____________________________________________________________________________*/

#define DO_NOT_INITIALIZE_CALIB_VALUE
#define DO_NOT_CLEAR_KPTVAL

section_layout :vtc:linear
{
	#ifdef DO_NOT_INITIALIZE_CALIB_VALUE
	
	// nocopy is added here to remove the ROM copy section for this initialized data
	// and the copy table entry
	group CALIBRATION_VALUE ( ordered, run_addr = mem:mpe:dspr0, nocopy )
	{
	   select ".data.TC397XP_TST.glb_calib_value";
	}
	
	#else
	
	group CALIBRATION_VALUE ( ordered, run_addr = mem:mpe:dspr0 )
	{
	   select ".data.TC397XP_TST.glb_calib_value";
	}
	
	#endif
	
	
	#ifdef DO_NOT_CLEAR_KPTVAL
	// the scratch attribute "s" is added here to prevent a copy table entry
	// to clear this section
	group NOT_CLEAR_KPTVAL ( ordered, run_addr = mem:mpe:dspr0, attributes = rws )
	{
	   select ".bss.TC397XP_TST.glb_keep_value";
	}
	
	#else
	
	group NOT_CLEAR_KPTVAL ( ordered, run_addr = mem:mpe:dspr0 )
	{
	   select ".bss.TC397XP_TST.glb_keep_value";
	}
	
	#endif
}

/*____________________________________________________________________________*/
/*____________________________________________________________________________*/

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