module pipeline_cpu(input clock, input reset);
// IF 阶段
wire [31:0] pc_current, npc;
pc pc_module(.pc(pc_current), .clock(clock), .reset(reset), .npc(npc));
wire [31:0] instruction;
im im_module(.instruction(instruction), .pc(pc_current));
wire [31:0] if_pc_plus_4 = pc_current + 4;
// IF/ID 寄存器
wire [31:0] id_pc_plus_4, id_instruction;
IF_ID if_id_reg(
.clock(clock),
.reset(reset),
.if_pc_plus_4(if_pc_plus_4),
.if_instruction(instruction),
.id_pc_plus_4(id_pc_plus_4),
.id_instruction(id_instruction)
);
// ID 阶段
wire [4:0] rs = id_instruction[25:21];
wire [4:0] rt = id_instruction[20:16];
wire [4:0] rd = id_instruction[15:11];
wire [5:0] opcode = id_instruction[31:26];
wire [5:0] funct = id_instruction[5:0];
// 控制信号生成（示例，需根据实际指令扩展）
wire reg_write = (opcode == 6'b000000) & (funct == 6'b100000); // ADD
wire mem_write = (opcode == 6'b101011); // SW
wire [3:0] alu_op = ...; // 根据指令设置ALU操作码
// 寄存器读取
wire [31:0] a, b;
gpr gpr_module(
.a(a),
.b(b),
.rs(rs),
.rt(rt),
.num_write(wb_rd),
.data_write(wb_data),
.reg_write(wb_reg_write),
.clock(clock)
);
// HILO读取（ID阶段）
wire [31:0] hilo_data;
hilo hilo_module(
.data_out(hilo_data),
.s(s_sel), // 根据指令选择HI/LO
.data_lo(wb_lo_data),
.data_hi(wb_hi_data),
.clock(clock),
.reset(reset),
.reg_write(wb_hilo_write)
);
// ID/EXE 寄存器
wire [31:0] exe_a, exe_b;
wire [4:0] exe_rd, exe_rt;
wire [3:0] exe_alu_op;
wire exe_reg_write, exe_mem_write;
ID_EXE id_exe_reg(
.clock(clock),
.reset(reset),
.id_pc_plus_4(id_pc_plus_4),
.id_a(a),
.id_b(b),
.id_rd(rd),
.id_rt(rt),
.id_alu_op(alu_op),
.id_reg_write(reg_write),
.id_mem_write(mem_write),
.exe_pc_plus_4(), // 未使用
.exe_a(exe_a),
.exe_b(exe_b),
.exe_rd(exe_rd),
.exe_rt(exe_rt),
.exe_alu_op(exe_alu_op),
.exe_reg_write(exe_reg_write),
.exe_mem_write(exe_mem_write)
);
// EXE 阶段
wire [31:0] alu_result;
alu alu_module(
.c(alu_result),
.a(exe_a),
.b(exe_b),
.op(exe_alu_op)
);
// EXE/MEM 寄存器
wire [31:0] mem_alu_result, mem_b;
wire [4:0] mem_rd;
wire mem_reg_write, mem_mem_write;
EXE_MEM exe_mem_reg(
.clock(clock),
.reset(reset),
.exe_alu_result(alu_result),
.exe_b(exe_b),
.exe_rd(exe_rd),
.exe_reg_write(exe_reg_write),
.exe_mem_write(exe_mem_write),
.mem_alu_result(mem_alu_result),
.mem_b(mem_b),
.mem_rd(mem_rd),
.mem_reg_write(mem_reg_write),
.mem_mem_write(mem_mem_write)
);
// MEM 阶段
wire [31:0] mem_data_out;
dm dm_module(
.data_out(mem_data_out),
.address(mem_alu_result),
.data_in(mem_b),
.mem_write(mem_mem_write),
.clock(clock)
);
// MEM/WB 寄存器
wire [31:0] wb_alu_result, wb_data_out;
wire [4:0] wb_rd;
wire wb_reg_write;
MEM_WB mem_wb_reg(
.clock(clock),
.reset(reset),
.mem_alu_result(mem_alu_result),
.mem_data_out(mem_data_out),
.mem_rd(mem_rd),
.mem_reg_write(mem_reg_write),
.wb_alu_result(wb_alu_result),
.wb_data_out(wb_data_out),
.wb_rd(wb_rd),
.wb_reg_write(wb_reg_write)
);
// WB 阶段
wire [31:0] wb_data = wb_reg_write ? (需要选择ALU结果或内存数据) ? wb_alu_result : wb_data_out;
assign wb_hi_data = ...; // 根据指令设置HI值
assign wb_lo_data = ...; // 根据指令设置LO值
assign wb_hilo_write = ...; // 根据指令类型生成写信号
endmodule
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