lightquantum的博客

ARMv7-M provides an interrupt controller as an integral part of the ARMv7-M exception model. ARMv7-M supports level-sensitivie and pulse-sensitive interrupt behavior.  Pulse interrupt sources mu

处理器有一个23位系统计时器，systick。 它从重载值开始向下计时，记到0时，在下一个时钟周期重载STK_LOAD寄存器的值，并开始新的时钟周期。 Relevant Registers: 相关寄存器: SysTick control and status register (STK_CTRL) Address offset: 0x00 Reset value: 0x0000